ADIN2111CCPZ-R7 datasheet(48/125 Pages) AD

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Data Sheet

ADIN2111

SWITCH SPI

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Rev. 0 | 48 of 125

2. Poll MDIOACC0. TRDONE= 0x1 to determine that the write

data operation is complete.

Example of Clause 22 read of Register XYZ:

1. Write MDIOACC0 with MDIO_DEV_AD = the address of the

MDIO_ST = 0x1(Clause 22), and TRDONE = 0x0.

2. Poll MDIOACC0. TRDONE = 0x1 to determine that the read

operation is complete. MDIO_DATA reflects the contents of

MDIO Register XYZ.

Example of Clause 22 write and read back of Register XYZ:

1. Write MDIOACC0 with MDIO_DATA = write data,

MDIO_DEV_AD = the address of the Register XYZ,

MDIO_PRTAD = 0x1, MDIO_OP = 0x1(WR), MDIO_ST =

0x1(Clause 22), and TRDONE = 0x0.

2. Write MDIOACC1 with MDIO_DEV_AD = the address of the

MDIO_ST = 0x1(Clause 22), and TRDONE = 0x0.

3. Poll MDIOACC1. TRDONE = 0x1 to determine that the read

operation is complete. MDIO_DATA reflects the contents of

MDIO Register XYZ.

Contents of PHY Registers

The PHY registers provide access to control and status information

in the management registers.

The registers of the PHY Clause 45 register map are made up of

four device address groupings (see Table 41) based on the MDIO

manageable device (MMD). Within each device address space,

IEEE standard registers are located in register addresses between

0x0000 and 0x7FFF, and vendor specific registers are located in

Table 41. Clause 45 Register Groupings

Device Address

MMD Name

0x01

PMA/physical medium dependent (PMD)

0x03

PCS

0x07

Autonegotiation

0x1E

Vendor Specific 1

Clause 45 can access to up to 32 PHYs consisting of up to 32

MMDs through a single MDIO interface.

The default value of some of the registers is determined by the

value of the hardware configuration pins, which are read just after

the RESET pin is deasserted. In these cases, the reset value in the

operation of the ADIN2111 to be configured without having to write

to it over the SPI.

Recommended Register Operation

Many of the PHY registers in the ADIN2111 are defined in the IEEE

Standard 802.3, and the exact behavior of these registers follows

the standard. This behavior is not always obvious and is described

in this section, in addition to the recommended operation and use of

the registers.

Latch Low Registers

The IEEE Standard 802.3-2018 requires certain MDIO accessi-

ble registers to exhibit latch low behavior. The idea is to allow

software that only intermittently reads these registers to detect

conditions that can be transitory or short lived. For example, the

AN_LINK_STATUS bit is required to latch low. When the device

exits from a reset or power-down state, the latching condition is not

active and the value of the AN_LINK_STATUS bit reflects the cur-

rent status of the link. However, if the link comes up and drops, the

latching condition is active. In this case, the AN_LINK_STATUS bit

reads as 0 even if the link has come back up again in the interim.

The latching condition is only cleared when the AN_LINK_STATUS

bit is read, ensuring the software had the opportunity to observe

that the link dropped.

One implication of this latch low behavior is that, if software wishes

to determine the current status of the link, it must perform two reads

of the AN_LINK_STATUS bit back to back. The first read is needed

to clear any active latching condition.

Another implication is that it is important that software take ac-

count of the interaction between MDIO accessible bits that share

a register address. For example, the AN_PAGE_RX bits and

AN_LINK_STATUS bits reside at the same register address. As

a result, reading the AN_PAGE_RX bits clears any active latching

condition associated with the AN_LINK_STATUS bits.

IEEE Duplicated Registers

The IEEE Standard 802.3-2018 covers a very wide range of stand-

ards and speeds, from 10 Mbps to 40 Gbps and higher, and

includes a large number of clauses. There are registers associated

with many clauses, and different PHYs can include different clauses

and combinations of clauses. Therefore, registers for common

functions like software reset, software power-down, loopback, and

so on, tend to be implemented in multiple clauses.

In the ADIN2111, the physical implementation of these registers is

in a single location, but they can be accessed at multiple address-

es. For example, the software reset bit, can be read or written in

all the following IEEE MMD locations and vendor specific register

locations:

►

PMA_SFT_RST

►

B10L_PMA_SFT_RST

►

PCS_SFT_RST

►

B10L_PCS_SFT_RST

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