ADIN2111CCPZ-R7 datasheet(70/125 Pages) AD

70 / 125 page

Data Sheet

ADIN2111

REGISTERS

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Rev. 0 | 70 of 125

When writing the ADDR_MSK_x registers, all two register locations must be written in order for a given table entry. They must be written in

order with the UPR register written first and the LWR register written last.

Table 80. Bit Descriptions for ADDR_MSK_LWRn

Bits

Bit Name

Description

Reset

Access

[31:0]

MAC_ADDR_MASK, Bits[31:0]

MAC Address Bit Mask for the Address Table.

0xFFFFFFFF

R/W

Time Stamp Accumulator Addend Register

Address: 0x80, Reset: 0x85555555, Name: TS_ADDEND

Table 81. Bit Descriptions for TS_ADDEND

Bits

Bit Name

Description

Reset

Access

[31:0]

TS_ADDEND

Time Stamp Accumulator Addend.

0x85555555

R/W

Timer Update Compare Register

Address: 0x81, Reset: 0x3B9ACA00, Name: TS_1SEC_CMP

Table 82. Bit Descriptions for TS_1SEC_CMP

Bits

Bit Name

Description

Reset

Access

[31:0]

TS_1SEC_CMP

Time Stamp 1 Second Compare Value.

0x3B9ACA00

R/W

Seconds Counter Register

Address: 0x82, Reset: 0x00000000, Name: TS_SEC_CNT

Use this register to write to the seconds counter.

Table 83. Bit Descriptions for TS_SEC_CNT

Bits

Bit Name

Description

Reset

Access

[31:0]

TS_SEC_CNT

Write to the Seconds Counter.

0x0

R/W

Nanoseconds Counter Register

Address: 0x83, Reset: 0x00000000, Name: TS_NS_CNT

Use this register to write to the nanoseconds counter.

Table 84. Bit Descriptions for TS_NS_CNT

Bits

Bit Name

Description

Reset

Access

[31:0]

TS_NS_CNT

Write to the Nanoseconds Counter. Note that this register must be programmed with a value that is divisible by

16 decimal. This is because the counters are driven by a 120 MHz clock and increment in steps of 16.

0x0

R/W

Timer Configuration Register

Address: 0x84, Reset: 0x00000000, Name: TS_CFG

Table 85. Bit Descriptions for TS_CFG

Bits

Bit Name

Description

Reset

Access

[31:5]

RESERVED

Reserved.

0x0

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