ADIN2111CCPZ-R7 datasheet(17/125 Pages) AD

17 / 125 page

Data Sheet

ADIN2111

THEORY OF OPERATION

analog.com

Rev. 0 | 17 of 125

Those conditions can be set to enable an interrupt on the INT

pin using the PHY subsystem interrupt mask register (PHY_SUB-

SYS_IRQ_MASK).

Following a hardware interrupt on the INT pin, the interrupt source

can be checked using the PHY subsystem interrupt status register

(PHY_SUBSYS_IRQ_STATUS).

Hardware Reset Interrupt

Each PHY of the ADIN2111 can also be configured to generate

a hardware interrupt after a hardware reset (RESET pin pulled

low) by setting the CRSM_HRD_RST_IRQ_EN bit in the system

interrupt mask register (CRSM_IRQ_MASK) of the respective PHY.

Although both PHYs can be used to generate a hardware interrupt,

it is recommended to use PHY 1 for this purpose.

Following a hardware interrupt received on the SPI host from the

INT pin, the PHYINT bit (respectively P2_PHYINT bit) on the Status

an interrupt from PHY 1 (respectively PHY 2).

The interrupt source can then be checked using the

CRSM_HRD_RST_IRQ_LH bit in the system interrupt status reg-

ister (CRSM_IRQ_STATUS) of the respective PHY.

Software Requested Interrupt

For system validation with an external host controller, each PHY of

the ADIN2111 can be requested to generate a hardware interrupt

on the INT pin using the CRSM_SW_IRQ_REQ bit in the system

interrupt mask register (CRSM_IRQ_MASK).

Although both PHYs can be used to generate a hardware interrupt,

it is recommended to use PHY 1 for this purpose.

Following a hardware interrupt received on the SPI host from the

INT pin, the PHYINT bit (respectively P2_PHYINT bit) in the Status

an interrupt from PHY 1 (respectively PHY 2).

The interrupt source can then be checked using the

CRSM_SW_IRQ_LH bit in the system interrupt status register

(CRSM_IRQ_STATUS) of the respective PHY.

PHY System Error Interrupts

Each of the ADIN2111 PHYs can also generate system errors

interrupts. The interrupt flags are located within the reserved bit

sections of system interrupt status register (CRSM_IRQ_STATUS)

of the respective PHY.

The system interrupt mask register (CRSM_IRQ_MASK) must be

configured on the respective PHY to allow system error interrupts.

Refer to Table 212 for details on the interrupts mask.

The ADIN2111 must be hardware reset to recover from a system

error interrupt from one of the two PHYs (CRSM_IRQ_STATUS

reserved bits read as 1 on the respective PHY).

RESET OPERATIONS

The ADIN2111 supports the following chip resets:

►

Power-on reset

►

Hardware reset

►

Software reset

►

MAC subsystem reset

►

PHY 1/PHY 2 subsystem reset

All of these resets put the ADIN2111, including the two PHY cores

and the internal switch, into a known state.

Power-On Reset

The ADIN2111 includes a power supply monitoring circuit to ensure

that the chip has the proper voltage supply before initiating the

power-up sequence. During power-up, the ADIN2111 is held in

hardware reset until each of the supplies crosses its minimum rising

threshold value and the power is considered good.

Hardware Reset

A hardware reset is initiated by the power-on reset circuitry or

by asserting the RESET pin low for a minimum of 10 µs. The

ADIN2111 includes deglitch circuitry on this pin to reject pulses

shorter than 1 µs.

When the RESET pin is deasserted, all the input/output (I/O) pins

are held in tristate mode, the hardware configuration pins are

latched, and the I/O pins are configured to their functional mode.

When all the external and internal supplies are valid and stable, the

crystal oscillator circuit is enabled. After the crystal starts up and

stabilizes, the phase-locked loop (PLL) enables. After a delay of

90 ms (maximum) from the deassertion of the RESET pin, all the

internal clocks are valid, the internal logic releases from reset, and

all the internal SPI, PHY 1, and PHY 2 registers are accessible from

the SPI.

The CLK25_REF clock output stays low while the RESET pin is

asserted low and remains low for another 70 ms (maximum) after

the RESET pin deasserts.

Software Reset

A chip software reset can be initiated by writing 1 to the SWRESET

field of the software reset register (SOFT_RST). Note that the

software reset does not reset PORT2 PHY. The PORT2 PHY can

be reset using the hardware reset or PHY subsystem reset.

If a transmission is taking place when the SPI software reset is

initiated, the frame transmission stops abruptly and a runt or a

ADIN2111CCPZ-R7 Folha de dados(PDF) 17 Page - Analog Devices

ADIN2111CCPZ-R7 Folha de dados(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL