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ADIN2111CCPZ-R7 Folha de dados(PDF) 117 Page - Analog Devices

Nome de Peças ADIN2111CCPZ-R7
Descrição Electrónicos  Low Complexity, 2-Port Ethernet Switch with Integrated 10BASE-T1L PHYs
PDF  125 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

ADIN2111CCPZ-R7 Folha de dados(HTML) 117 Page - Analog Devices

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Data Sheet
ADIN2111
REGISTERS
analog.com
Rev. 0 | 117 of 125
Table 232. Bit Descriptions for PHY_SUBSYS_IRQ_STATUS
Bits
Bit Name
Description
Reset
Access
15
RESERVED
Reserved.
0x0
R LH
14
MAC_IF_FC_FG_IRQ_LH
MAC Interface Frame Checker/Generator Interrupt.
0x0
R LH
13
MAC_IF_EBUF_ERR_IRQ_LH
MAC Interface Buffers Overflow/Underflow Interrupt.
0x0
R LH
12
RESERVED
Reserved.
0x0
R LH
11
AN_STAT_CHNG_IRQ_LH
Autonegotiation Status Change Interrupt.
0x0
R LH
[10:2]
RESERVED
Reserved.
0x0
R LH
1
LINK_STAT_CHNG_LH
Link Status Change.
0x0
R LH
0
RESERVED
Reserved.
0x0
R LH
PHY Subsystem Interrupt Mask Register
Device Address: 0x1F; Register Address: 0x0021, Reset: 0x2402, Name: PHY_SUBSYS_IRQ_MASK
Controls whether or not the interrupt signal is asserted in response to various events.
Table 233. Bit Descriptions for PHY_SUBSYS_IRQ_MASK
Bits
Bit Name
Description
Reset
Access
15
RESERVED
Reserved.
0x0
R/W SC
14
MAC_IF_FC_FG_IRQ_EN
Enable MAC Interface Frame Checker/Generator Interrupt.
0x0
R/W
13
MAC_IF_EBUF_ERR_IRQ_EN
Enable MAC Interface Buffers Overflow/Underflow Interrupt.
0x1
R/W
12
RESERVED
Reserved.
0x0
R/W
11
AN_STAT_CHNG_IRQ_EN
Enable Autonegotiation Status Change Interrupt.
0x0
R/W
[10:2]
RESERVED
Reserved.
0x100
R/W
1
LINK_STAT_CHNG_IRQ_EN
Enable Link Status Change Interrupt.
0x1
R/W
0
RESERVED
Reserved.
0x0
R/W
Frame Checker Enable Register
Device Address: 0x1F; Register Address: 0x8001, Reset: 0x0001, Name: FC_EN
This register is used to enable the frame checker. The frame checker analyzes the received frames from either the MAC interface or the PHY
(see the FC_TX_SEL register) to report the number of frames received, CRC errors, and various other frame errors. The frame checker frame
and error counter registers count these events.
Table 234. Bit Descriptions for FC_EN
Bits
Bit Name
Description
Reset
Access
[15:1]
RESERVED
Reserved.
0x0
R
0
FC_EN
Frame Checker Enable. Set to 1 to enable the frame checker.
0x1
R/W
Frame Checker Interrupt Enable Register
Device Address: 0x1F; Register Address: 0x8004, Reset: 0x0001, Name: FC_IRQ_EN
This register is used to enable the frame checker interrupt. An interrupt is generated when a receive error occurs. Enable the frame
checker/generator interrupt in the PHY_SUBSYS_IRQ_MASK register. Set the MAC_IF_FC_FG_IRQ_EN bit.
The status can be read via the MAC_IF_FC_FG_IRQ_LH bit in the PHY_SUBSYS_IRQ_STATUS register.



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