ADIN2111CCPZ-R7 datasheet(38/125 Pages) AD

38 / 125 page

Data Sheet

ADIN2111

SWITCH SPI

analog.com

Rev. 0 | 38 of 125

Table 34. Frame Header

D15 to D11

D10

D9 to D8

D7 to D6

D5 to D4

Reserved

Priority

Reserved

EGRESS_CAPTURE

Reserved

TIME_STAMP_PARITY

TIME_STAMP_PRESENT

Reserved

Port

See the following definitions:

►

Priority: indicates which priority queue the frame was received

from. Not used on transmit. Set 0 in transmitted frames.

►

EGRESS_CAPTURE: capture an egress time stamp into the

host readable egress time registers, as follows:

►

00: no action.

►

01: capture in the pair of the TTSCAL and TTSCAH registers.

The TTSCAA bits in the STATUS0 register assert when cap-

tured.

►

10: capture in the pair of the TTSCBL and TTSCBH registers.

The TTSCAB bits in the STATUS0 register assert when cap-

tured.

►

11: capture in the pair of the TTSCCL and TTSCCH registers.

The TTSCAC bits in the STATUS0 register assert when cap-

tured.

►

TIME_STAMP_PARITY: odd parity for the appended time stamp.

Not used on transmit. Set to 0 in transmitted frames.

►

TIME_STAMP_PRESENT: on receive, the first four bytes or eight

bytes of data contain the time stamp for the frame. Not used on

transmit. Set to 0 in transmitted frames.

►

Reserved: always set to 0.

Receive Frame over SPI

The following procedure (which applies to Port 1 and Port 2) must

be followed to receive an Ethernet frame when using the generic

SPI protocol in store and forward mode (the ADIN2111 operates in

store and forward mode by default):

1. Set the Px_RX_RDY_MASK bit to 0 to enable an interrupt when

a full frame is received.

2. If the Px_RX_RDY bit is asserted, read the MAC receive frame

size register to determine the size of the received frame.

3. Read the frame via the MAC receive register. It is possible to

burst read the entire frame or split it up into multiple smaller

burst reads. The first byte of the received frame is returned

in Px_RX, Bits[31:24]. The burst read transaction must be a

multiple of four bytes. Some of the last four bytes are padded

with 0s if the frame is not a multiple of four bytes in size.

4. Read Px_RX_RDY again. If the value of the bit is 1, another

frame is available to read. Repeat from Step 3.

Cut Through

The generic SPI protocol supports cut through mode for transmit

operations.

Before transmitting any frames, write 1 to the transmit cut through

enable bits.

The threshold at which the frame transmit starts can be

modified via the host transmit start threshold in cut through

bit (HOST_TX_THRESH) in the transmit threshold register

(TX_THRESH). This bit a default value of 1. Therefore, by default,

transmit starts immediately on writing to the host transmit FIFO.

To ensure that the frame transmission does not under run, the host

transmit FIFO has to be written at a rate greater than 10 Mbps. If

the frame under runs, the host transmit under run error bit asserts.

Generic SPI Errors

Generic SPI CRC Error

If an SPI CRC error occurs on a write to a register, the register is

not written.

If the write is to the transmit register, the transmit FIFO is missing

data and must be cleared by the host. Similarly, a read of the

receive register has missing data in the receive frame, and the

FIFO must be cleared.

If the errored transaction was a write to a configuration register, the

SPI host must issue the write again. If the software does not know

which configuration, reset the MAC by writing the RST_MAC_ONLY

keys to the SOFT_RST register.

Generic SPI Transmit Protocol Error (TXPE)

TXPE asserts when the TX_FSIZE register is written, but the MAC

still expects further writes to the transmit register related to the

previous frame size written to the TX_FSIZE register. This error

does not occur in the normal operation and indicates an issue

with the software driver, for example, two consecutive writes to the

TX_FSIZE register without any writes to the transmit register.

In response to the assertion of TXPE, the host must clear the

transmit FIFO.

OPEN ALLIANCE SPI PROTOCOL

The OPEN Alliance SPI protocol Version 1.0 can transfer data

over the SPI using full duplex operation, achieving a 10-Mbps

bidirectional frame transfer with an SPI clock frequency in the

region of 12 MHz to 16 MHz or greater.

The ADIN2111 supports the following OPEN Alliance SPI capabili-

ties. See the supported capabilities register (CAPABILITY) for more

details:

►

Transmit FCS validation

►

Cut through

►

IEEE 1588 time stamp capture on transmit and receive

►

Minimum supported chunk size is 8 bytes

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