ADIN2111CCPZ-R7 datasheet(86/125 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Rev. 0 | 86 of 125

Table 157. Bit Descriptions for MI_STATUS

Bits

Bit Name

Description

Reset

Access

MI_EXT_STAT_SPRT

Extended Status Support. The extended status support bit always reads as 0 to indicate that

the PHY does not provide extended status information in Register 0xF.

0x0

MI_UNIDIR_ABLE

Unidirectional Ability. The unidirectional ability register always reads as 0 to indicate that the

PHY can only transmit data from the MII when it determines that a valid link is established.

0x0

MI_MF_PREAM_SUP_ABLE

Management Preamble Suppression Ability. The management frame preamble suppression

ability bit always reads as 0 to indicate that the PHY is not able to receive management

frames that are not preceded by the preamble pattern.

0x0

MI_AN_COMPLETE

Autonegotiation Complete. The autonegotiation complete bit indicates that the autonegotia-

tion process completed and the PHY link is up. Mirrors AN_COMPLETE.

0x0

MI_REM_FLT

Remote Fault. The remote fault bit always reads as 0 because the PHY has no provision for

remote fault detection.

0x0

R LH

MI_AN_ABLE

Autonegotiation Ability. The autonegotiation ability bit always reads as 1 indicating that the

PHY has the ability to perform autonegotiation. Mirrors AN_ABLE.

0x1

MI_LINK_STAT_LAT

Link Status. This bit uses a latch low functionality as described in IEEE Standard 802.3

Subclause 45.2.7.20.5. If the link status value is fail, this register stays cleared and remains

cleared until the latching is cleared when the register is read. Mirrors AN_LINK_STATUS.

0x0

R LL

MI_JABBER_DET

MII Jabber Detect. The jabber detect bit always reads as 0 because the 10BASE-T1L PHY

does not incorporate a jabber detect function.

0x0

R LH

MI_EXT_CAPABLE

MII Extended Capability. The extended capability bit always reads as 1 indicating that the

PHY provides an extended set of capabilities that can be accessed through the extended

0x0, 0x1, and 0xF.

0x1

PHY Identifier 1 Register

Address: 0x2, Reset: 0x0283, Name: MI_PHY_ID1

The PHY Identifier 1 address allows 16 bits of the OUI to be observed.

Table 158. Bit Descriptions for MI_PHY_ID1

Bits

Bit Name

Description

Reset

Access

[15:0]

MI_PHY_ID1

The PHY Identifier 1 address allows 16 bits of the OUI to be observed.

0x283

PHY Identifier 2 Register

Address: 0x3, Reset: 0xBC01, Name: MI_PHY_ID2

The PHY Identifier 2 address allows six bits of the OUI, and the model and revision number to be observed.

Table 159. Bit Descriptions for MI_PHY_ID2

Bits

Bit Name

Description

Reset

Access

[15:10]

MI_PHY_ID2_OUI

OUI, Bits[7:2].

0x2F

[9:4]

MI_MODEL_NUM

Model Number.

Pin dependent

[3:0]

MI_REV_NUM

Revision Number.

0x1

MMD Access Control Register

Address: 0xD, Reset: 0x0000, Name: MMD_ACCESS_CNTRL

This address corresponds to the MMD access control register specified in Clause 22.2.4.3.11 of IEEE Standard 802.3-2018.

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