PC87307 datasheet(11/218 Pages) NSC

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7.13.3

Shadow of FIFO Control Register (SH_FCR), Bank 3, Offset 02h ............................ 157

7.13.4

Link Control Register (LCR) and Bank Select Register (BSR), Bank 3, Offset 03h .. 157

7.14

BANK 4 – IR MODE SETUP REGISTER ................................................................................ 157

7.14.1

Reserved Registers, Bank 4, Offsets 00h and 01h ................................................... 157

7.14.2

Infrared Control Register 1 (IRCR1), Bank 4, Offset 02h .......................................... 157

7.14.3

Link Control Register (LCR) and Bank Select Register (BSR), Bank 4, Offset 03h .. 158

7.14.4

Reserved Registers, Bank 4, Offsets 04h -07h ......................................................... 158

7.15

BANK 5 – INFRARED CONTROL REGISTERS ..................................................................... 158

7.15.1

Reserved Registers, Bank 5, Offsets 00h -02h ......................................................... 158

7.15.2

(LCR/BSR) Register, Bank 5, Offset 03h .................................................................. 158

7.15.3

Infrared Control Register 2 (IRCR2), Bank 5, Offset 04h .......................................... 158

7.15.4

Reserved Registers, Bank 5, Offsets 05h -07h ......................................................... 158

7.16

BANK 6 – INFRARED PHYSICAL LAYER CONFIGURATION REGISTERS ......................... 159

7.16.1

Infrared Control Register 3 (IRCR3), Bank 6, Offset 00h .......................................... 159

7.16.2

Reserved Register, Bank 6, Offset 01h ..................................................................... 159

7.16.3

SIR Pulse Width Register (SIR_PW), Bank 6, Offset 02h ......................................... 159

7.16.4

Link Control Register (LCR) and Bank Select Register (BSR), Bank 6, Offset 03h .. 159

7.16.5

Reserved Registers, Bank 6, Offsets 04h-07h .......................................................... 159

7.17

BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS 159

7.17.1

Infrared Receiver Demodulator Control Register (IRRXDC), Bank 7, Offset 0 ......... 160

7.17.2

Infrared Transmitter Modulator Control Register (IRTXMC), Bank 7, Offset 01h ...... 160

7.17.3

Consumer-IR Configuration Register (RCCFG), Bank 7, Offset 02h ........................ 163

7.17.4

Link Control/Bank Select Registers (LCR/BSR), Bank 7, Offset 03h ........................ 163

7.17.5

Infrared Interface Configuration Register 1 (IRCFG1), Bank 7, Offset 04h ............... 163

7.17.6

Reserved Register, Bank 7, Offset 05h ..................................................................... 164

7.17.7

Infrared Interface Configuration 3 Register (IRCFG3), Bank 7, Offset 06h ............... 164

7.17.8

Infrared Interface Configuration Register 4 (IRCFG4), Bank 7, Offset 07h ............... 164

7.18

UART2 REGISTER WITH FAST IR REGISTER BITMAPS .................................................... 165

8.0

General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip

Select Output Signals

8.1

GENERAL PURPOSE INPUT AND OUTPUT (GPIO) PORTS ............................................... 170

8.2

PROGRAMMABLE CHIP SELECT OUTPUT SIGNALS ......................................................... 171

9.0

Power Management (Logical Device 8)

9.1

POWER MANAGEMENT OPTIONS ....................................................................................... 172

9.1.1

Configuration Options ................................................................................................ 172

9.1.2

The WATCHDOG Feature ......................................................................................... 172

9.2

THE POWER MANAGEMENT REGISTERS .......................................................................... 172

9.2.1

Power Management Index Register, Base Address + 00h ........................................ 172

9.2.2

Power Management Data Register, Base Address + 01h ......................................... 173

9.2.3

Function Enable Register 1 (FER1), Index 00h ......................................................... 173

9.2.4

Function Enable Register 2 (FER2), Index 01h ......................................................... 173

9.2.5

Power Management Control 1 Register (PMC1), Index 02h ..................................... 174

9.2.6

Power Management Control 2 Register (PMC2), Index 03h ..................................... 174

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