PC87307 datasheet(36/218 Pages) NSC

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Configuration

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FIGURE 2-5. Programmable Chip Select Conﬁguration

Index Register Bitmap

2.4.6

Programmable Chip Select Configuration Data

This read/write register contains the data in the Program-

mable Chip Select Configuration register (see Section 2.10)

indicated by the Programmable Chip Select Configuration

Index register at index 23h.

FIGURE 2-6. Programmable Chip Select Conﬁguration

Data Register Bitmap

2.4.7

SRID Register (In PC97307 only)

This read-only register contains the identity number of the

chip revision. SRID is incremented on each tapeout.

FIGURE 2-7. SRID Register Bitmap

Index of a Programmable

Read Only

76543210

Reset

Required

Programmable Chip Select

Index 23h

Configuration Index

Chip Select Configuration

Data in a Programmable

76543210

Reset

Required

Programmable Chip Select

Index 24h

Configuration Data

Chip Select Configuration

76543210

Reset

Required

SRID Register,

Index 27h

(In PC97307 only)

Chip Revision ID

2.5

KBC CONFIGURATION REGISTER (LOGICAL

DEVICE 0)

2.5.1

SuperI/O KBC Configuration Register,

Index F0h

This read/write register is reset by hardware to 40h.

FIGURE 2-8. SuperI/O KBC Conﬁguration Register

Bitmap

Bits 5-0 - Reserved

Reserved.

Bits 7,6 - KBC Clock Source

Bit 6 is the LSB. The clock source can be changed only

when the KBC is inactive (disabled).

00 - 8 MHz

01 - 12 MHz

10 - 16 MHz. Undeﬁned results when these bits are 10

and the clock source for the chip is 24 MHz on X1.

11 - Reserved.

2.6

FDC CONFIGURATION REGISTERS (LOGICAL

DEVICE 3)

2.6.1

SuperI/O FDC Configuration Register,

Index F0h

This read/write register is reset by hardware to 20h.

FIGURE 2-9. SuperI/O FDC Conﬁguration Register Bit-

map

Reserved

KBC Clock Source

76543210

Reset

Required

SuperI/O KBC

Index F0h

Configuration

TRI-STATE Control

Four Drive Control

76543210

Reset

Required

Super I/O FDC

Index F0h

Configuration

Reserved

DENSEL Polarity Control

TDR Register Mode

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