PC87307 datasheet(46/218 Pages) NSC

46 / 218 page

Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)

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External

TEST1

3-State

5-Cycle

32-Bit

Timer

Prescaler

8-Bit Timer

or Counter

Overflow

Flag

Stop

Counter

Timer

Counter

Interrupt

(MCLK)

Frequency

X1C

X2C

External

32768 Hz

Crystal

External Event Input

24 or 48 MHz

Clock

KBC Clock

Clock

Select

48 MHz

2 or 3

÷ 2

Select

Frequency

Multiplier

(1465)

Source

FIGURE 3-6. Timing Generation and Timer Circuit

3.3.4

Timer or Event Counter

The keyboard controller includes an 8-bit counter, which

can be used as a timer or an event counter, as selected by

the firmware.

Timer Operation

When the internal clock is chosen as the counter input, the

counter functions as a timer. The clock fed to the timer con-

sists of the KBC instruction cycle clock, divided by 32. (See

Figures 3-4 and 3-6.) The divisor is reset only by a hardware

reset or when the timer is started by an STRT T instruction.

The timer counts up from a programmable initial value and

sets an overflow flag when it overflows. This flag may be

tested, or may be set up to generate an overflow interrupt.

Refer to the 8042 or PC87323VUL instruction set for details.

Event Counter Operation

When the clock input of the counter is switched to the exter-

nal input (MCLK), it becomes an event counter. The falling

edge of the signal on the MCLK pin causes the counter to

increment. Timer Overflow Flag and Timer interrupt operate

as in the timer mode.

3.4

EXTERNAL I/O INTERFACES

The PC chipset interfaces with the part as illustrated in Fig-

ure 3-2 on page 44.

All data transactions between the KBC and the PC chipset

are handled by the part.

The part decodes all I/O device chip-select functions from

the address bus. The KBC chip-select codes are, tradition-

ally, 60h or 64h, as described in Table 3-1. (These address-

es are user-programmable.)

The external interface includes two sets of signals: the key-

board and mouse interface signals, and the general-pur-

pose I/O signals.

3.4.1

Keyboard and Mouse Interface

Four serial I/O signals interface with the external keyboard

and mouse. These signals are driven by open-collector driv-

ers with signals derived from two I/O ports residing on the

internal bus. Each output can drive 16 mA, making them

suitable for driving the keyboard and mouse cables. The

signals are named KBCLK, KBDAT, MCLK and MDAT, and

they are the logical complements of P26, P27, P23 and

P22, respectively.

TEST0 and TEST1 are dedicated test pins, internally con-

nected to KBCLK and MCLK, respectively, as shown in Fig-

ures 3-1 and 3-2. These pins may be used as logical

conditions for conditional jump instructions, which directly

check the logical levels at the pins.

KBDAT and MDAT are connected to pins P10 and P11, re-

spectively.

MCLK also provides input to the event counter.

3.4.2

General Purpose I/O Signals

The P12, P16, P17, P20 and P21 general purpose I/O sig-

nals interface to two I/O ports (port1 and port2). P12, P16

and P17 are mapped to port 1 and P20 and P21 are

mapped to port 2.

P12, P16 and P17 are driven by quasi-bidirectional drivers.

(See Figure 3-7.) These signals are called quasi-bidirec-

tional because the output buffer cannot be turned off (even

when the I/O signal is used for input).

During output, a 1 written to output is strongly pulled up for

the duration of a (short) write pulse, and thereafter main-

tained by a high impedance “weak” active pull-up (imple-

mented by a degenerated transistor employed as a

switchable pull-up resistor). A series resistor to those port

lines used for input is recommended to limit the surge cur-

rent during the strong pull-up. See Figure 3-8.

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