| Os motores de busca de Datasheet de Componentes eletrônicos |
|
PC87307 Folha de dados(PDF) 30 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC87307 Folha de dados(HTML) 30 Page - National Semiconductor (TI) |
|
30 / 218 page ![]() 30 Configuration www.national.com 2.3.2 Configuration Register Summary The tables in this section specify the Index, type (read/write), reset value and configuration register or action that controls each register associated with each function. When the reset value is not fixed, the table indicates what controls the value or points to another section that provides this information. Soft Reset is related to a Reset executed by utilizing the Reset Bit (Bit 0) of the Config Control Register. (See Table 2-5 on page 27.) TABLE 2-11. Card Configuration Registers TABLE 2-12. KBC Configuration Registers for Keyboard - Logical Device 0 Index Type Hard Reset Soft Reset Configuration Register or Action 00h W 00h PnP ISA Set RD_DATA Port. 01h R Serial Isolation. 02h W PnP ISA PnP ISA Configuration Control. 03h W 00h PnP ISA Wake[CSN]. 04h R Resource Data. 05h R Status. 06h R/W 00h PnP ISA Card Select Number (CSN). 07h R/W 00h PnP ISA Logical Device Number. 20h R See section 2.4.1 and 2.4.2 on page 34. SID Register. 21h R/W See Section 2.4.3 on page 34. No Effect SuperI/O Configuration 1 Register. 22h R/W See Section 2.4.4 on page 35. No Effect SuperI/O Configuration 2 Register. 23h R/W See Section 2.4.5 on page 35. No Effect Programmable Chip Select Configuration Index Register. 24h R/W See Section 2.4.6 on page 36. No Effect Programmable Chip Select Configuration Data Register. 27h R See Section 2.4.7 on page 36. SRID Register (in pc97307 only). Index R/W Hard Reset Soft Reset Configuration Register or Action 30h R/W 00h or 01h See CFG0, Section 2.1.3. 00h or 01h See CFG0,Section 2.1.3. Activate. See also FER1 of power management device (logical device 8). 31h R/W 00h 00h I/O Range Check. 60h R/W 00h 00h Data Base Address MSB Register. 61h R/W 60h 60h Data Base Address LSB Register. Bit 2 (for A2) is read only, 0. 62h R/W 00h 00h Command Base Address MSB Register. 63h R/W 64 64h Command Base Address LSB. Bit 2 (for A2) is read only,1. 70h R/W 01h 01h KBC Interrupt (KBC IRQ1 pin) Select. 71h RW 02h 02h KBC Interrupt Type. Bits 1,0 are read/write; other bits, read only. 74h R 04h 04h Report no DMA assignment. 75h R 04h 04h Report no DMA assignment. F0h R/W See Section 2.5.1 on page 36. No Effect SuperI/O KBC Configuration Register. |
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |