PC87307 datasheet(59/218 Pages) NSC

59 / 218 page

Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)

www.national.com

Power Off Request (POR)

The APC allows a maskable or non-maskable interrupt on

the POR pin when the Switch Off event is detected on the

SWITCH input pin.

This interrupt enables the user to perform an orderly exit

procedure, automatically performing housekeeping func-

tions such as file backups, printout completion and commu-

nications terminations, before powering down.

See Figure 4-10.

Power Failure

The APC is in a Power Failure state when it is powered by

VBAT, without VCCH.

Upon entering a Power Failure state, the following events

occur:

• The UART input signals (RI2,1), the SWITCH (ON/OFF

switch) pin and RING pin (for detecting telephone line

incoming signals for fax, modem or voice communica-

tions) are masked (high).

These signals remain masked until one second after exit

from the Power Failure state, i.e., one second after

switching from VBAT to VCCH, unless the MOAP bit is set

to 1. See description of this bit on page 60..

• The ONCTL pin state is internally saved, and ONCTL is

forced inactive.

One second after power returns, the ONCTL signal re-

verts to its saved state, if the MOAP bit (Mask ONCTL

Activation, i.e., bit 4) of the APCR1 register is cleared

to 0. If the MOAP bit is set to 1, ONCTL remains inac-

tive. If MOAP = 0, when the one second delay expires,

new events can activate ONCTL, unless a time match

occurs during Power Failure, in which case the APC

“remembers” to activate ONCTL at the end of the one

second delay.

If the MOAP bit (bit 4 of APCR1) and the Power Failure

bit (bit 7 of APCR1) are both 1, then only the Switch On

event can activate ONCTL.

4.4.3

System Power-Up and Power-Off Activation

Event Description

The APC may activate the host power supply when the fol-

lowing events occur:

• Physical On/Off switch is depressed and V

DD is ab-

sent.

• Preprogrammed wake-up time arrives.

• Communications input is detected on a modem.

• Ring signal is detected at a telephone input jack.

The PC may be powered down by the following events:

• Physical On/Off switch is depressed, and V

DD is

present.

• Software controlled power down.

• Fail-safe power down in the event of power-down soft-

ware hang-up. (See “Switch-Off Event”.)

The SWITCH Input Signal

This signal provides two events: Switch-On and Switch-Off.

In both, the physical switch line is debounced, i.e., the sig-

nal state is transferred only after 14 to 16 msec without tran-

sitions, which ensures the switch is no longer bouncing. See

Figure 4-10.

Switch-On Event - Detection of a high to low transition on

the debounced SWITCH input pin, when VDD does not

exist. The Switch-On event is masked (not detected) for

one to two seconds after VDD is removed.

Switch-Off Event - Detection of a high to low transition on

the debounced SWITCH input pin, when VDD exists.

The Switch-Off event is masked for one to two seconds

after VDD was removed for the last time.

The Switch-Off event sets the Switch-Off Event Detect

bit (bit 5 in APSR) to 1.

Switch-Off Delay - When the Switch Off Delay Enable bit

(bit 6 in register APCR2) is 0, the Switch-Off event pow-

ers the system off immediately, i.e., the ONCTL output

pin is deactivated immediately.

When the Switch-Off Delay Enable bit is 1 and a Switch-Off

event occurs, a fail-safe timer starts a countdown of 5 or 21

seconds. (See bit 1 of the APCR1 register on page 60). If it

is allowed to complete this sequence, the fail-safe timer sets

the ONCTL signal high (inactive).

Switch-Off Event detection activates the Power-Off Re-

quest (POR) that triggers a user-defined interrupt routine to

conduct housekeeping activities prior to powering down.

(The user may also detect the Switch-Off Event by polling

the Switch-Off Detect bit, rather than the interrupt routine).

The user must ensure that the power-off routine does not

exceed the 5 or 21 second Switch-Off Delay, or else the

routine must set bit 6 of APCR1 to stop and reset the fail-

safe timer, thus preventing fail-safe timer causing power off

before completion.

If the power-off routine gets “hung up”, and the timer was

not stopped and reset, then after the delay time has elapsed

the timer will conclude its countdown and activate power off

(deactivate ONCTL).

The fails-safe timer is reset and stopped by writing 1 to the

Fail-safe Timer Reset bit (bit 6 of APCR1). Switch-Off

events detected while the timer is already counting are ig-

nored. If during the count of the Fail-safe timer due to a

switch off event with delay, VDD goes down, the fail safe

timer is stopped and reset and ONCTL is not deactivated.

POR is asserted on a Switch-Off Event. It can be configured

as either edge or level triggered, according to the APCR1

level mode it remains asserted until cleared by a level POR

Clear Command (bit 3 of the APCR1 register, see Figure

4-10). Selection of POR on the GPIO22/POR pin is via the

SuperI/O Configuration 2 register (at index 22h). Selection

of the POR output buffer is via GPIO22 output buffer control

bits (Port 2 Output Type and Port 2 Pull-up Control regis-

ters). See Table 8-1 on page 170.

PC87307 Folha de dados(PDF) 59 Page - National Semiconductor (TI)

PC87307 Folha de dados(HTML) 59 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL