PC87307 datasheet(97/218 Pages) NSC

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Eighth Command Phase Byte - Bytes Between Sectors

- Gap 3

The value in this byte specifies how many bytes there

are between sectors. See “Fifth Command Phase Byte

- Bytes in Gap 3” on page 90.

Ninth Command Phase Byte - Data Length (Obsolete)

The value in this byte is ignored and must be set to FFh.

Execution Phase

In this phase, data read from the disk drive is transferred to

the system via DMA or non-DMA modes. See 5.4.2 on page

78.

The controller looks for the track number specified in the

third command phase byte. If implied seeks are enabled,

the controller also performs all operations of a SENSE IN-

TERRUPT command and of a SEEK command (without is-

suing these commands). Then, the controller waits the head

settle time. See bits 3-0 of the fourth command phase byte

of the MODE command on page 94.

The controller then starts the data separator and waits for

the data separator to find the address field of the next sec-

tor. The controller compares the ID information (track num-

ber, head number, sector number, bytes-per-sector code) in

that address field with the corresponding information in the

command phase bytes of the READ DATA command.

If the contents of the bytes do not match, then the controller

waits for the data separator to find the address field of the

next sector. The process is repeated

until a match or an

error occurs.

Possible errors, the conditions that may have caused them

and the actions that result are:

• The microprocessor aborted the command by writing to

the FIFO.

If there is no disk in the drive, the controller gets stuck.

The microprocessor must then write a byte to the FIFO

to advance the controller to the result phase.

• Two pulses of the INDEX signal were detected since the

search began, and no valid ID was found.

If the track address differs, either the Wrong Track bit

(bit 4) or the Bad Track bit (bit 1) (if the track address is

FFh) is set in result phase Status register 2 (ST2). See

Section 5.5.3 on page 82.

If the head number, sector number or bytes-per-sector

code did not match, the Missing Data bit (bit 2) is set in

result phase Status register 1 (ST1).

If the Address Mark (AM) was not found, the Missing Ad-

dress Mark bit (bit 0) is set in ST1.

Section 5.5.2 on page 81 describes the bits of ST1.

• A CRC error was detected in the address field. In this

case the CRC Error bit (bit 5) is set in ST1.

Once the address field of the desired sector is found, the

controller waits for the data separator to find the data field

for that sector.

If the data field (normal or deleted) is not found within the

expected time, the controller terminates the operation, en-

ters the result phase and sets bit 0 (Missing Address Mark)

in ST1.

If a deleted data mark is found, and Skip (SK) control is set

to 1 in the opcode command phase byte, the controller skips

this sector and searches for the next sector address field as

described above. The effect of Skip Control (SK) on the

READ DATA command is summarized in Table 5-17.

TABLE 5-17. Skip Control Effect on READ DATA

Command

After finding the data field, the controller transfers data

bytes from the disk drive to the host until the bytes-per-sec-

tor count has been reached, or until the host terminates the

operation by issuing the Terminal Count (TC) signal, reach-

ing the end of the track or reporting an overrun.

See also, Section “The Phases of FDC Commands” on

page 78.

The controller then generates a Cyclic Redundancy Check

(CRC) value for the sector and compares the result with the

CRC value at the end of the data field.

After reading the sector, the controller reads the next logical

sector unless one or more of the following termination con-

ditions occurs:

• The DMA controller asserted the Terminal Count (TC)

signal to indicate that the operation terminated. The In-

terrupt Code (IC) bits (bits 7,6) in ST0 are set to normal

termination (00). See page 81.

• The last sector address (of side 1, if the Multi-Track en-

able bit (MT) was set to 1) was equal to the End of Track

sector number. The End of Track bit (bit 7) in ST1 is set.

The IC bits in ST0 are set to abnormal termination (01).

This is the expected condition during non-DMA trans-

fers.

• Overrun error. The Overrun bit (bit 4) in ST1 is set. The

Interrupt Code (IC) bits (bits 7,6) in ST0 are set to abnor-

mal termination (01). If the microprocessor cannot ser-

vice a transfer request in time, the last correctly read

byte is transferred.

• CRC error. CRC Error bit (bit 5) in ST1 and CRC Error

in Data Field bit (bit 5) in ST2, are set. The Interrupt

Code (IC) bits (bits 7,6) in ST0 are set to abnormal ter-

mination (01).

If the Multi-Track (MT) bit was set in the opcode command

byte, and the last sector of side 0 has been transferred, the

controller continues with side 1.

Skip

Control

(SK)

Data

Type

Sector

Read?

Control

Mark Bit 6

of ST2

Result

Normal

Termination

Deleted

No More

Sectors Read

Normal

Termination

Deleted

Sector Skipped

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