PC87307 datasheet(67/218 Pages) NSC

67 / 218 page

The Digital Floppy Disk Controller (FDC) (Logical Device 3)

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PC-AT Drive Mode

The PC-AT register set is enabled. The DMA enable bit in

the Digital Output Register (DOR) becomes valid (the ap-

propriate IRQ and DRQ signals can be put in TRI-STATE).

TC and DENSEL become active high signals (default to a

5.25" floppy disk drive).

PS/2 Drive Mode

This drive mode supports the PS/2 models 50/60/80 config-

uration and register set. The value of the DMA enable bit in

the Digital Output Register (DOR) becomes unimportant

(the IRQ and DRQ signals assigned to the FDC are always

valid). TC and DENSEL become active low signals (default

to 3.5" floppy drive).

5.2

DATA TRANSFER

5.2.1

Data Rates

The FDC supports the standard PC data rates of 250, 300

and 500 Kbps, as well as 1 Mbps. High performance tape

and floppy disk drives that are currently emerging in the PC

world, transfer data at 1 Mbps. The FDC also supports the

perpendicular recording mode, a new format used for some

high capacity disk drives at 1 Mbps.

The internal digital data separator needs no external com-

ponents. It improves the window margin performance stan-

dards of the DP8473, and is compatible with the strict data

separator requirements of floppy disk drives and tape

drives.

The FDC contains write precompensation circuitry that de-

faults to 125 nsec for 250, 300, and 500 Kbps (41.67 nsec

at 1 Mbps). These values can be overridden in software to

disable write precompensation or to provide levels of pre-

compensation up to 250 nsec.

The FDC has internal 24 mA data bus buffers which allow

direct connection to the system bus. The internal 40 mA to-

tem-pole disk interface buffers are compatible with both

CMOS drive input signals and 150 resistor terminated disk

drive input signals.

5.2.2

The Data Separator

The internal data separator is a fully digital PLL. The fully

digital PLL synchronizes the raw data signal read from the

disk drive. The synchronized signal is used to separate the

encoded clock and data pulses. The data pulses are broken

down into bytes, and then sent to the microprocessor by the

controller.

The FDC supports data transfer rates of 250, 300, 500 Kbps

and 1 Mbps in Modified Frequency Modulation (MFM) for-

mat.

The FDC has a dynamic window margin and lock range per-

formance capable of handling a wide range of floppy disk

drives. In addition, the data separator operates under a va-

riety of conditions, including high fluctuations in the motor

speed of tape drives that are compatible with floppy disk

drives.

The dynamic window margin is the primary indicator of the

quality and performance level of the data separator. It indi-

cates the toleration of the data separator for Motor Speed

Variation (MSV) of the drive spindle motor and bit jitter (or

window margin).

Figure 5-2 shows the dynamic window margin in the perfor-

mance of the FDC at different data rates, generated using a

FlexStar FS-540 floppy disk simulator and a proprietary dy-

namic window margin test program written by National

Semiconductor.

FIGURE 5-2. PC87307/PC97307 Dynamic Window Mar-

gin Performance

The x axis measures MSV. MSV is translated directly to the

actual rate at which the data separator reads data from the

disk. In other words, a faster than nominal motor results in

a higher data rate.

The dynamic window margin performance curve also indi-

cates how much bit jitter (or window margin) can be tolerat-

ed by the data separator. This parameter is shown on the y-

axis of the graph. Bit jitter is caused by the magnetic inter-

action of adjacent data pulses on the disk, which effectively

shifts the bits away from their nominal positions in the mid-

dle of the bit window. Window margin is commonly mea-

sured as a percentage. This percentage indicates how far a

data bit can be shifted early or late with respect to its nomi-

nal bit position, and still be read correctly by the data sepa-

rator. If the data separator cannot correctly decode a shifted

bit, then the data is misread and a CRC error results.

The dynamic window margin performance curve supplies

two pieces of information:

• The maximum range of MSV (also called “lock range”)

that the data separator can handle with no read errors.

• The maximum percentage of window margin (or bit jit-

ter) that the data separator can handle with no read er-

rors.

Thus, the area under the dynamic window margin curves in

Figure 5-2 is the range of MSV and bit jitter that the FDC can

handle with no read errors. The internal digital data separa-

tor of the FDC performs much better than comparable digi-

tal data separator designs, and does not require any

external components.

-14 -12 -10 -8 -6 -4 -2 0

8 10 12 14

Motor Speed Variation (% of Nominal)

250,300, 500 Kbps and 1 Mbps

Typical Performance at 500 Kbps,

VDD = 5.0 V, 25° C

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