PC87307 datasheet(100/218 Pages) NSC

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5.7.13

The READ A TRACK Command

The READ A TRACK command reads sectors from the se-

lected drive, in physical order, and makes the data available

to the host.

Command Phase

The command phase bytes of the READ A TRACK com-

mand are like those of the READ DATA command, except

for the MT and SK bits. Multi-track and skip operations are

not allowed in the READ A TRACK command. Therefore,

bits 7 and 5 of the opcode command phase byte (MT and

SK, respectively) must be 0.

First Command Phase Byte, Opcode

See “Bit 6 - Modified Frequency Modulation (MFM)” on

page 90.

Second Command Phase Byte

See “Second Command Phase Byte” on page 90 for a

description of the Drive Select (DS1,0) and Head Select

(HD) bits.

See “Bit 5 - Implied Seek (IPS)” on page 93 for a de-

scription of the Implied Seek (IPS) bit.

Third through Ninth Command Phase Bytes

See “The READ DATA Command” on page 96.

Execution Phase

Data read from the disk drive is transferred to the system in

DMA or non-DMA modes. See Section 5.4.2.

Execution of this command is like execution of the READ

DATA command except for the following differences:

• The controller waits for a pulse from the INDEX signal

before it searches for the address field of a sector.

If the microprocessor writes to the FIFO before the IN-

DEX pulse is detected, the command enters the result

phase with the Interrupt Code (IC) bits (bits 7,6) in ST0

set to abnormal termination (01).

• All the ID bytes of the sector address are compared, ex-

cept the sector number. Instead, the sector number is

set to 1, and then incremented for each successive sec-

tor read.

• If no match occurs when the ID bytes of the sector ad-

dress are compared, the controller sets the Missing

76543210

MFM

000010

IPS

XXXX

DS1

DS0

Track Number

Head Number

Sector Number

Bytes-Per-Sector Code

End of Track (EOT) Sector Number

Bytes Between Sectors - Gap 3

Data Length (Obsolete)

Data bit (bit 2) in ST1, but continues to read the sector.

If there is a CRC error in the address field being read,

the controller sets CRC Error (bit 5) in ST1, but contin-

ues to read the sector.

• If there is a CRC error in the data field, the controller

sets the CRC Error bit (bit 5) in ST1 and CRC Error in

Data Field bit (bit 5) in ST2, but continues reading sec-

tors.

• The controller reads a maximum of End of Track (EOT)

physical sectors. There is no support for multi-track

reads.

Result Phase

5.7.14

The RECALIBRATE Command

The RECALIBRATE command issues pulses that make the

head of the selected drive step out until it reaches track 0.

Command Phase

Second Command Phase Byte

See “Second Command Phase Byte” on page 90 for a

description of the Drive Select (DS1,0) and Head Select

(HD) bits.

Execution Phase

After the last command byte is issued, the Drive Busy bit for

the selected drive is set in the Main Status Register (MSR).

See bits 3-0 in “Main Status Register (MSR), Offset 04h,

Read Operations” on page 74.

The controller waits the Delay Before Processing time (see

Table 5-25 on page 106) for the selected drive., and then

becomes idle. See “Idle Phase” on page 80.

Then, the controller issues pulses until the TRK0 disk inter-

face input signal becomes active or until the maximum num-

ber of RECALIBRATE step pulses have been issued.

Table 5-20 shows the maximum number of RECALlIBRATE

step pulses that may be issued, depending on the RECAL-

IBRATE Step Pulses (R255) bit, bit 0 in the second com-

mand phase byte of the MODE command (page 92), and

the Extended Track Range (ETR) bit, bit 4 of the third com-

mand byte of the MODE command (page 93).

76543210

Result Phase Status Register 0 (ST0)

Result Phase Status Register 1 (ST1)

Result Phase Status Register 2 (ST2)

Track Number

Head Number

Sector Number

Bytes-Per-Sector Code

76543210

00000111

XXXXX

DS1

DS0

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