ADP1052ACPZ-R7 datasheet(24/113 Pages) AD

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ADP1052

Data Sheet

Rev. B | Page 24 of 113

The PWM settings of open-loop operation are different from those

of general closed-loop operation.

Set the rising edge timings and falling edge timings by

using Register 0xFE3E to Register 0xFE4F. Typically, a duty

cycle setting of ~50% is recommended for ease of zero-

voltage-switching operation. A phase shift function of 180° is

preferred to guarantee balanced PWM outputs.

Program Register 0xFE3C to a value of 0x00, which sets the

modulation limit to 0 μs.

Apply negative modulation to the falling edges of all PWM

outputs, OUTA to OUTD (or just one pair of them), for soft

start. The soft start of SR1 and SR2 is not recommended.

Write 111111 binary to Register 0xFE67[5:0] to set all PWM

channels to follow open-loop operation. Set Register 0xFE09[7]

to enable the soft start procedure. The soft start speed is

specified by Register 0xFE09[4:3].

Always set Register 0xFE09[2] = 1. The soft start ramp

time is determined by tF2 − tR2.

Because the output voltage is not regulated, some of the settings,

such as the VOUT setting, digital compensator settings, and constant

current control, are not functional. Other settings can be pro-

grammed to be similar to those of general closed-loop operation.

CURRENT SENSE

The ADP1052 has two current sense inputs: CS1 (Pin 6) and

CS2− and CS2+ (Pin 3 and Pin 4, respectively). These inputs

sense, protect, and control the primary side input current and the

secondary side output current. They can be calibrated to reduce

errors caused by the external components.

CS1 Operation (CS1 Pin)

Current Sense 1 (CS1) is typically used for the monitoring and

protection of the primary side current, which is commonly

sensed using a current transformer (CT). The input signal at the

CS1 pin is fed into an ADC for current monitoring. The range of

the ADC is 0 V to 1.60 V. The input signal is also fed into an

analog comparator for cycle-by-cycle current limiting and IIN

overcurrent fast protection, with a reference of 0.25 V or 1.2 V set

by Register 0xFE1B[6]. The typical configuration for the CS1

current sense is shown in Figure 25.

REFERENCE

REG 0xFE1B[6]

12 BITS

CYCLE-BY-CYCLE

CURRENT LIMITING

AND IIN FAST OCP

CS1

ADC

VIN

Figure 25. CS1 Operation

The CS1 ADC measures the average value of the primary side

current. The ADC samples at a frequency of 1.56 MHz and

reports a CS1 reading (12 bits) in the READ_IIN command

(Register 0x89), with an asynchronously averaged rate of 10 ms,

63 ms, 126 ms, 252 ms, or 504 ms set by Register 0xFE65[2:0].

Various IIN overcurrent fast fault limits and response actions can

be set for CS1. These are described in the Current Sense and

Limit Setting Registers section.

CS2 Operation (CS2−, CS2+ Pins)

Current Sense 2 (CS2) is typically used for the monitoring and

protection of the output current. The full-scale range of the CS2

ADC is 120 mV. The differential inputs are fed into an ADC

through a pair of external resistors that provide the necessary

level shifting. The CS2+ and CS2− device pins are regulated to

approximately 1.12 V by internal current sources.

Depending on the configuration of the current sense resistor,

the ADP1052 must be programmed in low-side mode or high-

side mode, using Register 0xFE19[7]. Typical configurations are

shown in Figure 26 and Figure 27.

When using low-side current sensing, as shown in Figure 26,

the current sources are 225 μA. Therefore, the required resistor

value is 1.12 V/225 μA = 4.98 kΩ, and 4.99 kΩ resistors are

preferred.

VOUT

CS2–

CS2+

ADC

12 BITS

ADP1052

225µA

Figure 26. CS2 Low-Side Resistive Current Sense

When using high-side current sensing, as shown in Figure 27,

the current sources are 1.915 mA. Therefore, the required resistor

value is (VOUT − 1.12 V)/1.915 mA. If VOUT = 12 V, 5.62 kΩ resistors

are required.

VOUT

CS2+

CS2–

ADC

12 BITS

ADP1052

1.915mA

Figure 27. CS2 High-Side Resistive Current Sense

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