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Data Sheet

ADP1052

Rev. B | Page 39 of 113

CS3 Overcurrent Protection

CS3 overcurrent protection provides alternative output overcurrent

protection if the CS2 current sense is not available. The reading

is calculated from the CS1 and duty cycle readings.

The CS3_OC_FAULT flag (Register 0xFEA0[3]) is set when

the CS3 current reading of the eight most significant bits (MSBs)

in Register 0xFEA9 exceeds the CS3_OC_FAULT_LIMIT that is

programmed in Register 0xFE6A. The debounce time of the flag

setting can be programmed at 0 ms, 10 ms, 20 ms, or 200 ms in

is programmed in the CS3_OC_FAULT_RESPONSE bits

(Register 0xFE01[3:0]). See the Manufacturer Specific Protection

Responses section and the register settings for specific action

information.

Synchronous Rectification (SR) Reverse Current

Protection

In SR applications, the reverse current may flow from VOUT

through the output inductor, SRs, and current sense resistor to

ground. If the SRs are turned off during a large reverse current

condition, the high voltage stress caused by the large di/dt of

current flowing into the output inductor may damage the

synchronous rectifiers.

An analog comparator with programmable references

implements the SR reverse current detection. The reverse current

protection limit, SR_RC_FAULT_LIMIT, is programmed using

the CS2− pin (Pin 3) and CS2+ pin (Pin 4) falls below the value

programmed in Register 0xFE1A[2:0], the SR_RC_FAULT flag

is triggered. The debounce time for triggering the SR_RC_FAULT

flag is 40 ns or 200 ns, set by Register 0xFE1A[3].

DEBOUNCE

REG 0xFE1A[3]

SR_RC_FAULT

FLAG

REG 0xFEA1[5]

VOUT

CS2–

CS2+

ADC

12 BITS

ADP1052

225µA

SR_RC_FAULT_LIMIT

REG 0xFE1A[2:0]

Figure 42. SR FET Reverse Current Protection

To suppress the reverse current, the SR_RC_FAULT flag

response is set in the SR_RC_FAULT_ RESPONSE bits

(Register 0xFE03[7:4]). In addition to the three response options

of continuing operation without interruption, disabling SR1 and

SR2, and disabling all the PWM outputs, there is a fourth fault

response mode: changing the rising edge position of SR1 and

SR2. Using this protection mode, the rising edges of SR1 and SR2

each maintain a fixed value, effective from the next switching

cycle (typically SR1 and SR2 are set to 50% duty cycle for best

performance). The fixed values of the rising edge timings for SR1

and SR2 can be determined as follows:

tRx + tMODU_LIMIT − tOFFSET

where:

tRx is the timing of the rising edges of SR1 and SR2 (see Figure 68).

tMODU_LIMIT is the modulation limit defined in Register 0xFE3C.

tOFFSET is the offset setting in Register 0xFE68.

After the fault flag is cleared, SR1 and SR2 can be set to return

immediately to normal condition or follow the soft recovery

process, as specified in Register 0xFE03[5:4]. For the best

reverse current protection performance, use the previously

defined settings to fine tune the SR1 and SR2 PWM timing.

Using this protection mode to set the 50% duty cycle operation

of the SR1 and SR2 signals discharges energy in the output back

to the input and suppresses the reverse current. Accordingly, the

drain to source voltage (VDS) stress of the synchronous rectifiers is

suppressed. See the Manufacturer Specific Protection Responses

section and the register settings for specific action information.

FLAGIN Protection

The SYNI/FLGI pin (Pin 13) can be configured in flag input mode

(FLGI). An external signal can be sent to the ADP1052 to trigger

an action. The polarity of the external signal is configured by the

FLGI polarity bit (Register 0xFE12[2]). When the ADP1052

detects an external signal, the FLAGIN flag is set. The response to

the FLAGIN flag is programmed in the FLAGIN_RESPONSE

bits (Register 0xFE03[3:0]). See the Manufacturer Specific

Protection Responses section and the register settings for the

more information about the actions that can be programmed.

VDD OVLO Protection

The ADP1052 has built-in overvoltage protection (OVP) on

its supply rail. The VDD overvoltage response bits (VDD_OV_

RESPONSE), found in Register 0xFE05[5:4], are used to specify

the response to a VDD overvoltage condition.

If Register 0xFE05[5] = 0, the VDD_OV flag is set and the

ADP1052 shuts down when the VDD voltage rises above the

OVLO threshold. When the VDD overvoltage condition ends,

the VDD_OV flag is cleared and the ADP1052 downloads

the EEPROM contents before restarting with a soft start

process. Program the debounce time of the VDD_OV flag

using Register 0xFE05[4].

If Register 0xFE05[5] = 1, the VDD_OV flag is always cleared,

regardless of VDD voltage conditions. The ADP1052 continues to

operate without interruption. However, programming the

VDD_OV flag response as always cleared is not recommended.

MANUFACTURER SPECIFIC PROTECTION

RESPONSES

For the VDD_OV flag and protection action, see the VDD

OVLO Protection section.

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