ADP1052ACPZ-R7 datasheet(90/113 Pages) AD

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ADP1052

Data Sheet

Rev. B | Page 90 of 113

Table 133. Register 0xFE1C—PWM Outputs Disable Settings at Deep Light Load Mode

Bits

Bit Name/Function

R/W

Description

[7:6]

Reserved

R/W

Reserved.

SR2 disable

R/W

Setting this bit disables the SR2 output when operating in deep light load mode.

SR1 disable

R/W

Setting this bit disables the SR1 output when operating in deep light load mode.

OUTD disable

R/W

Setting this bit disables the OUTD output when operating in deep light load mode.

OUTC disable

R/W

Setting this bit disables the OUTC output when operating in deep light load mode.

OUTB disable

R/W

Setting this bit disables the OUTB output when operating in deep light load mode.

OUTA disable

R/W

Setting this bit disables the OUTA output when operating in deep light load mode.

Table 134. Register 0xFE1D—Matched Cycle-by-Cycle Current-Limit Settings

Bits

Bit Name/Function

R/W

Description

Reserved

R/W

Reserved.

Enable matched cycle-by-cycle current

limit

R/W

Setting this bit enables the matched cycle-by-cycle current-limit function.

[5:4]

Select PWM output pairs for matched

cycle-by-cycle current limit

R/W

These bits select the PWM pairs for matched cycle-by-cycle current limiting.

Bit 5

Bit 4

PWM Pairs

OUTB and OUTD

OUTA and OUTC

OUTC and OUTD

OUTA and OUTB

OUTD rising edge blanking

R/W

This bit specifies whether the blanking time for the CS1 cycle-by-cycle current-

limit comparator is referenced to the rising edge of OUTD.

0 = no blanking at the OUTD rising edge.

1 = blanking time referenced to the OUTD rising edge.

OUTC rising edge blanking

R/W

This bit specifies whether the blanking time for the CS1 cycle-by-cycle current-

limit comparator is referenced to the rising edge of OUTC.

0 = no blanking at the OUTC rising edge.

1 = blanking time referenced to the OUTC rising edge.

OUTB rising edge blanking

R/W

This bit specifies whether the blanking time for the CS1 cycle-by-cycle current-

limit comparator is referenced to the rising edge of OUTB.

0 = no blanking at the OUTB rising edge.

1 = blanking time referenced to the OUTB rising edge.

OUTA rising edge blanking

R/W

This bit specifies whether the blanking time for the CS1 cycle-by-cycle current-

limit comparator is referenced to the rising edge of OUTA.

0 = no blanking at the OUTA rising edge.

1 = blanking time referenced to the OUTA rising edge.

Table 135. Register 0xFE1E—Light Load Mode and Deep Light Load Mode Settings

Bits

Bit Name/Function

R/W

Description

[7:6]

CS2 averaging speed for

drooping control

R/W

These bits set the CS2 (output current) averaging speed and resolution used for the drooping

control. Faster speed corresponds to lower resolution and, therefore, lowers accuracy of the

drooping line.

Bit 7

Bit 6

Speed (μs)

Resolution (Bits)

164

328

656

[5:4]

Light load mode and deep

light load mode averaging

speed

R/W

These bits set the averaging speed and resolution used for the light load mode threshold and

deep light load mode threshold. Faster speed corresponds to lower resolution and, therefore,

to lower accuracy of the threshold.

Bit 5

Bit 4

Speed (μs)

Resolution (Bits)

164

328

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