ADP1052ACPZ-R7 datasheet(16/113 Pages) AD

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ADP1052

Data Sheet

Rev. B | Page 16 of 113

Figure 13. PWM Settings for Zero-Voltage-Switched Full Bridge Topology with Synchronous Rectification Using the ADP1052 GUI

The advantage of the SR soft start is that it minimizes the

output voltage undershoot that occurs when the SR FETs are

turned on without a soft start. The advantage of immediately

and completely turning on the SRx signals is that they help

minimize the voltage transient caused during a load step.

Using Register 0xFE08[4], the SR soft start can be programmed

to occur one time only (the first time that the SRx signals are

enabled) or every time that the SRx signals are enabled (for

example, when the system enters or exits deep light load mode).

When programming the ADP1052 to use the SR soft start,

ensure the correct operation of this function by setting the

falling edge of SR1 (tF5) to a lower value than the rising edge of SR1

(tR5) and setting the falling edge of SR2 (tF6) to a lower value than

the rising edge of SR2 (tR6). During the SR soft start, the rising

edges of SRx move gradually from the right side (the tRX +

tMODU_LIMIT position) to the left side to increase the duty cycle.

The ADP1052 is well suited for dc-to-dc converters in isolated

topologies. Every time a PWM signal crosses the isolation

barrier, a propagation delay is added because of the isolating

components. Using Register 0xFE3A[5:0], an adjustable delay

(0 ns to 315 ns in steps of 5 ns) can be programmed to move

both SR1 and SR2 later in time to compensate for the added

propagation delay. In this way, all the PWM edges can be aligned

(see Figure 68).

PWM MODULATION LIMIT AND 180° PHASE SHIFT

The modulation limit register (Register 0xFE3C, see Table 159) can

be programmed to apply a maximum modulation limit to any

PWM signal, thus limiting the modulation range of any PWM

output. If modulation is enabled, the maximum modulation

limit is applied to all PWM outputs collectively. This limit,

tMODU_LIMIT, is the maximum time variation for the modulated

edges from the default timing, following the configured

modulation direction (see Figure 14).

tRX

tFX

tRY

tFY

OUTX

OUTY

tMODU_LIMIT

tS/2

Figure 14. Setting Modulation Limits

There is no setting for the minimum duty cycle limit. Therefore,

the user must set the rising edges and falling edges based on the

case with the least amount of modulation.

Each least significant bit (LSB) in Register 0xFE3C corresponds

to a different time step size, depending on the switching

frequency (see Table 159). If the ADP1052 is to control a dual-

ended topology (such as full bridge, half bridge, or push pull),

enable the dual-ended topology mode using Register 0xFE13[6];

thus, the modulation limit in each half cycle is one half of the

modulation value programmed by Register 0xFE3C.

The modulated edges cannot go beyond one switching cycle. To

extend the modulation range for some applications, the 180° phase

shift can be enabled using Register 0xFE3B[5:0].

When the 180° phase shift is disabled, the rising edge timing

and the falling edge timing are referred to the start of the switching

cycle (see tRX and tFX in Figure 14). When the 180° phase shift is

enabled, the rising edge timing and the falling edge timing are

referred to half of the switching cycle (see tRY and tFY in Figure 14,

which are referred to tS/2). Therefore, when the 180° phase shift

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