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ADP1052ACPZ-R7 Folha de dados(PDF) 4 Page - Analog Devices |
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ADP1052ACPZ-R7 Folha de dados(HTML) 4 Page - Analog Devices |
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4 / 113 page  ADP1052 Data Sheet Rev. B | Page 4 of 113 SPECIFICATIONS VDD = 3.0 V to 3.6 V, TJ = −40°C to +125°C, unless otherwise noted; FSR = full-scale range. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SUPPLY Supply Voltage VDD 3.0 3.3 3.6 V 2.2 μF capacitor connected to AGND Supply Current IDD 33 mA Normal operation; PWM pins unloaded IDD + 6 mA During EEPROM programming 50 100 μA Shutdown; VDD below undervoltage lockout (UVLO) POWER-ON RESET Power-On Reset 3.0 V VDD rising UVLO Threshold UVLO 2.75 2.85 2.97 V VDD falling UVLO Hysteresis 35 mV Overvoltage Lockout (OVLO) Threshold OVLO 3.7 3.9 4.1 V OVLO Debounce 2 μs VDD_OV flag debounce set to 2 μs 500 μs VDD_OV flag debounce set to 500 μs VCORE PIN Output Voltage VCORE 2.45 2.6 2.75 V 330 nF capacitor connected to AGND OSCILLATOR AND PLL PLL Frequency 190 200 210 MHz RES input = 10 kΩ (±0.1%) Digital PWM Resolution 625 ps OUTA, OUTB, OUTC, OUTD, SR1, SR2 PINS Output Voltage Low VOL 0.4 V IOH = 10 mA High VOH VDD − 0.4 V IOL = −10 mA Rise Time tR 3.5 ns CLOAD = 50 pF Fall Time tF 1.5 ns CLOAD = 50 pF Output Current Source IOL −10 mA Sink IOH 10 mA Synchronization Signal Output (SYNO) Positive Pulse Width 600 640 680 ns OUTC or OUTD programmed as SYNO VS+, VS− VOLTAGE SENSE PINS Input Voltage Range VIN 0 1 1.6 V Differential voltage from VS+ to VS− Leakage Current 1.0 μA Voltage Sense (VS) Accurate Analog-to- Digital Converter (ADC) Valid Input Voltage Range 0 1.6 V ADC Clock Frequency 1.56 MHz Register Update Rate 10 ms Measurement Resolution 12 Bits Accuracy Factory trimmed at 1.0 V −5 +5 % FSR 0% to 100% of input voltage range −80 +80 mV −2 +2 % FSR 10% to 90% of input voltage range −32 +32 mV −1.0 +1.0 % FSR 900 mV to 1.1 V −16 +16 mV Temperature Coefficient 70 ppm/°C Voltage Differential from VS− to AGND −200 +200 mV |
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