ADP1052ACPZ-R7 datasheet(15/113 Pages) AD

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Data Sheet

ADP1052

Rev. B | Page 15 of 113

PWM OUTPUTS (OUTA, OUTB, OUTC, OUTD, SR1,

AND SR2)

The PWM outputs control the primary side drivers and the

synchronous rectifier drivers. They can be used for several

topologies, such as hard-switched full bridge, zero-voltage-switched

full bridge, phase shifted full bridge, half bridge, push pull, two-

switch forward, active clamp forward, and interleaved buck.

Delays between rising and falling edges are individually

programmable. Special care is required to avoid shoot through and

cross conduction. The ADP1052 GUI software is recommended

to program these outputs.

Figure 12 shows an example configuration to drive a zero-

voltage-switched full bridge topology with synchronous

rectification. The QA, QB, QC, QD, QSR1, and QSR2 switches

are driven separately by the PWM outputs (OUTA, OUTB,

OUTC, OUTD, SR1, and SR2). Figure 13 shows an example of

PWM settings for the power stage shown in Figure 12.

All PWM and SRx outputs are synchronized with each other.

Therefore, when reprogramming more than one of these

outputs, it is important to first update all of the registers and

then latch the information into the shadow registers simulta-

neously. During the reprogramming operation, the outputs are

temporarily disabled.

To ensure that new PWM timings and the switching frequency

setting are programmed simultaneously, a special instruction is

sent to the ADP1052 by setting Register 0xFE61[2:1] (the GO

commands, see Table 181). It is recommended to disable the PWM

outputs that are not in use via Register 0xFE53[5:0]. See the

PWM Outputs Timing Registers section for additional

information about the PWM timings.

SYNCHRONOUS RECTIFICATION

SR1 and SR2 are recommended to serve as the PWM control

signals when synchronous rectification is in use. These PWM

signals can be configured much like the other PWM outputs.

An optional soft start can be applied to the SR PWM outputs.

Use Register 0xFE08[4:0] to program the SR soft start.

When the SR soft start is disabled (Register 0xFE08[1:0] = 00), the

SRx pin signals are immediately turned on to their modulated

PWM duty cycle values.

When the SR soft start is enabled (Register 0xFE08[1:0] = 11),

the SR1 and SR2 rising edges move left from the tRX + tMODU_LIMIT

position to the tRX + tMODULATION position in steps that are set in

rising edge timing of SR1 (tR5) and the rising edge timing of SR2

(tR6) (see Figure 68); tMODU_LIMIT represents the modulation limit

defined in Register 0xFE3C (see Figure 67); tMODULATION represents

the real-time modulation value.

The SR soft start is applicable even when the SR1 and SR2 pins

are not programmed for modulation. When the SR soft start is

enabled, the SR1 and SR2 rising edges move left from the tRX +

tMODU_LIMIT position to the tRX position in steps that are set in

ISOLATOR

DRIVER

OUTA

OUTB

OUTC

OUTD

SR1

SR2

VIN

QSR2

QSR1

DRIVER

Figure 12. PWM Assignment for Zero-Voltage-Switched Full Bridge Topology with Synchronous Rectification

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