ADP1052ACPZ-R7 datasheet(100/113 Pages) AD

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ADP1052

Data Sheet

Rev. B | Page 100 of 113

Table 169. Register 0xFE55—Volt-Second Balance Control on OUTA and OUTB

Bits

Bit Name/Function

R/W

Description

tR2 balance setting

R/W

Setting this bit enables modulation from balancing control on the OUTB rising edge, tR2.

tR2 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tR2 right.

1 = negative sign. Increase of balancing control modulation moves tR2 left.

tF2 balance setting

R/W

Setting this bit enables modulation from balancing control on the OUTB falling edge, tF2.

tF2 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tF2 right.

1 = negative sign. Increase of balancing control modulation moves tF2 left.

tR1 balance setting

R/W

Setting this bit enables modulation from balancing control on the OUTA rising edge, tR1.

tR1 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tR1 right.

1 = negative sign. Increase of balancing control modulation moves tR1 left.

tF1 balance setting

R/W

Setting this bit enables modulation from balancing control on the OUTA falling edge, tF1.

tF1 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tF1 right.

1 = negative sign. Increase of balancing control modulation moves tF1 left.

Table 170. Register 0xFE56—Volt-Second Balance Control on OUTC and OUTD

Bits

Bit Name/Function

R/W

Description

tR4 balance setting

R/W

Setting this bit enables modulation from balancing control on the OUTD rising edge, tR4.

tR4 balance setting

R/W

0 = positive sign. Increase of balancing control modulation moves tR4 right.

1 = negative sign. Increase of balancing control modulation moves tR4 left.

tF4 balance setting

R/W

Setting this bit enables modulation from balancing control on the OUTD falling edge, tF4.

tF4 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tF4 right.

1 = negative sign. Increase of balancing control modulation moves tF4 left.

tR3 balance setting

R/W

Setting this bit enables modulation from balancing control on the OUTC rising edge, tR3.

tR3 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tR3 right.

1 = negative sign. Increase of balancing control modulation moves tR3 left.

tF3 balance setting

R/W

Setting this bit enables modulation from balancing control on the OUTC falling edge, tF3.

tF3 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tF3 right.

1 = negative sign. Increase of balancing control modulation moves tF3 left.

Table 171. Register 0xFE57—Volt-Second Balance Control on SR1 and SR2

Bits

Bit Name/Function

R/W

Description

tR6 balance setting

R/W

Setting this bit enables modulation from balancing control on the SR2 rising edge, tR6.

tR6 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tR6 right.

1 = negative sign. Increase of balancing control modulation moves tR6 left.

tF6 balance setting

R/W

Setting this bit enables modulation from balancing control on the SR2 falling edge, tF6.

tF6 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tF6 right.

1 = negative sign. Increase of balancing control modulation moves tF6 left.

tR5 balance setting

R/W

Setting this bit enables modulation from balancing control on the SR1 rising edge, tR5.

tR5 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tR5 right.

1 = negative sign. Increase of balancing control modulation moves tR5 left.

tF5 balance setting

R/W

Setting this bit enables modulation from balancing control on the SR1 falling edge, tF5.

tF5 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tF5 right.

1 = negative sign. Increase of balancing control modulation moves tF5 left.

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