ADP1052ACPZ-R7 datasheet(86/113 Pages) AD

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ADP1052

Data Sheet

Rev. B | Page 86 of 113

SWITCHING FREQUENCY AND SYNCHRONIZATION REGISTERS

When synchronization is enabled, the ADP1052 takes the SYNI signal and adds the tSYNC_DELAY, together with a 760 ns propagation delay, to

generate the internal synchronization reference clock as shown in Figure 65. The ADP1052 uses the reference clock to generate its own clock.

760ns +

tSYNC_DELAY

CLOCKSYNC

SYNI

Figure 65. Synchronization Timing

Table 123. Register 0xFE11—Synchronization Delay Time

Bits

Bit Name/Function

R/W

Description

[7:0]

tSYNC_DELAY

R/W

Sets the additional delay of the synchronization reference clock to the rising edge of the SYNI pin

signal. Each LSB size is 40 ns. Note that this delay time cannot exceed one switching period. If the

PWM 180° phase shift is enabled, this delay time cannot exceed one-half of one switching period.

Table 124. Register 0xFE12—Synchronization General Settings

Bits

Bit Name/Function

R/W

Description

Reserved

R/W

Reserved.

Phase capture range

for synchronization

R/W

Sets the phase capture range. The ADP1052 detects the phase shift between the external and internal

clocks when synchronization function is enabled. When the phase shift falls within the range,

synchronization starts.

0 = phase capture range is ±3.125% (±11.25°).

1 = phase capture range is ±6.25% (±22.5°). This is the recommended setting.

OUTD used as SYNO

R/W

0 = OUTD is used as the PWM output.

1 = OUTD is used as SYNO output.

OUTC used as SYNO

R/W

0 = OUTC is used as PWM output.

1 = OUTC is used as SYNO output.

Enable

synchronization

R/W

Setting this bit enables frequency synchronization as a slave device. The ADP1052 synchronizes with the

external clock through the SYNI/FLGI pin. Bit 0 = 0 when synchronization is enabled.

FLGI polarity

R/W

Sets the polarity for the SYNI/FLGI pin when the pin is programmed as FLGI.

0 = a high logic level on the FLGI pin sets the FLAGIN flag; a low logic level clears the FLAGIN flag.

1 = a low logic level on the FLGI pin sets the FLAGIN flag; a high logic level sets the FLAGIN flag.

FLAGIN flag

debounce time

R/W

0 = 0 μs debounce time for the FLAGIN flag.

1 = 100 μs debounce time for the FLAGIN flag.

SYNI/FLGI pin

function selection

R/W

Configures the SYNI/FLGI pin as a flag input or a synchronization input. When SYNI is not enabled,

this bit must be set to 1.

0 = the SYNI/FLGI pin is used as the synchronization input (SYNI).

1 = the SYNI/FLGI pin is used as the flag input (FLGI).

Table 125. Register 0xFE13—Dual-Ended Topology Mode

Bits

Bit Name/Function

R/W

Description

Reserved

R/W

Reserved.

Dual-ended

topology enable

R/W

To use dual-ended topologies, set this bit to 1. It affects the modulation high limit. The modulation

limit in each half cycle is one-half of the modulation limit that is programmed in Register 0xFE3C.

0 = operates in single-ended topologies, such as buck, forward, and flyback.

1 = operates in dual-ended topologies, such as full bridge, half bridge, and push pull.

[5:0]

Reserved

R/W

Reserved.

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