ADP1052ACPZ-R7 datasheet(21/113 Pages) AD

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Data Sheet

ADP1052

Rev. B | Page 21 of 113

ADP1052

LOAD

DIGITAL

COMPENSATOR

VS+

VS–

VOLTAGE SENSE

REGISTERS

HIGH SPEED

ADC

VOUT_UV_FAULT FLAG

VOUT_UV_FAULT_LIMIT

ACCURATE

ADC

Figure 20. Voltage Sense Configuration

Voltage Sense ADCs

Two varieties of sigma-delta (Σ-Δ) ADCs are used in the

ADP1052 feedback loop, as follows:



Low frequency ADC, running at 1.56 MHz



High frequency ADC, running at 25 MHz

The Σ-Δ ADCs have a resolution of one bit and operate

differently from traditional flash ADCs. The equivalent

resolution that can be obtained depends on the length of time

the output bit stream of the Σ-Δ ADC is filtered.

The Σ-Δ ADCs also differ from Nyquist rate ADCs in that the

quantization noise is not uniform across the frequency spectrum.

At lower frequencies, the noise decreases. At higher frequencies,

the noise increases (see Figure 21).

FREQUENCY

NYQUIST ADC

NOISE

Σ-∆ ADC

NOISE

Figure 21. ADC Noise Performance

The low frequency ADC runs at approximately 1.56 MHz. For

a specified bandwidth, the equivalent resolution is calculated as

ln(1.56 MHz/BW)/ln(2) = N bits

For example, at a bandwidth of 95 Hz, the equivalent

resolution/noise is

ln(1.56 MHz/95 Hz)/ln(2) = 14 bits

At a bandwidth of 1.5 kHz, the equivalent resolution/noise is

ln(1.56 MHz/1.5 kHz)/ln(2) = 10 bits

The high frequency ADC has a 25 MHz clock. It is comb filtered

and outputs at the switching frequency into the digital compen-

sator. See Table 5 for the equivalent resolution at selected

sampling frequencies.

Table 5. Equivalent Resolutions for High Frequency ADC

at Selected Switching Frequencies

fSW (kHz)

High Frequency ADC Resolution (Bits)

49 to 87

97.5 to 184

195.5 to 379

390.5 to 625

The high frequency ADC has a range of ±25 mV. Using a base

switching frequency of 97.5 kHz at an 8-bit high frequency

ADC resolution, the quantization noise is 0.195 mV.

1 LSB = 2 × 25 mV/28 = 0.195 mV

When the switching frequency increases to 195.5 kHz at a 7-bit

high frequency ADC resolution, the quantization noise is 0.391 mV

(1 LSB = 2 × 25 mV/27 = 0.391 mV). Increasing the switching fre-

quency to 390.5 kHz increases the quantization noise to 0.781 mV,

as follows:

1 LSB = 2 × 25 mV/26 = 0.781 mV

Output Voltage Adjustment Commands

In the ADP1052, the voltage data for commanding or reading

the output voltage or related parameters is in linear data format.

The linear format exponent is fixed at −10 decimal (see the

VOUT_MODE command, Register 0x20, in Table 22).

The following three basic commands are used for setting the

output voltage:



VOUT_COMMAND command (Register 0x21, Table 23)



VOUT_MARGIN_HIGH command (Register 0x25, Table 27)



VOUT_MARGIN_LOW command (Register 0x26, Table 28)

One of these three values is selected by the OPERATION

command (Register 0x01, Table 14).

The VOUT_MAX command (Register 0x24, Table 26) sets an

upper limit on the output voltage that the ADP1052 can

command, regardless of any other commands or combinations.

During output voltage adjustment, use the VOUT_TRANSITION_

RATE command (Register 0x27, Table 29) to set the rate (in mV/μs)

at which the VS± pins change voltage.

DIGITAL COMPENSATOR

Use the internal programmable digital compensator to change the

control loop of the power supply. A Type III digital compensator

architecture is implemented in this device. This Type III

compensator is reconstructed by a low frequency filter with

input from the low frequency ADC and a high frequency filter

with input from the high frequency ADC.

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