ADP1052ACPZ-R7 datasheet(81/113 Pages) AD

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Data Sheet

ADP1052

Rev. B | Page 81 of 113

Table 112. Register 0xFE03—Flag Response Register Bit Descriptions

Bits

Bit Name/Function

R/W

Description

[7:6]

Fault response

R/W

These bits specify the action when the flag is set.

Bit 7

Bit 6

Fault Response

Continues operation without interruption.

Disables SR1 and SR2.

Disables all PWM outputs.

The rising edges of SR1 and SR2 move to tRx + tMODU_LIMIT − tOFFSET. See the

Synchronous Rectification (SR) Reverse Current Protection section for more

information.

[5:4]

Action after the fault

flag is cleared

R/W

These bits specify the action when the flag is cleared.

Bit 5

Bit 4

Bits[7:6] = 01 or 10

Bits[7:6] = 11

After the flag reenable delay time, the PWM

outputs are reenabled with a soft start.

SR1 and SR2 follow the soft recovery

process.

The PWM outputs are reenabled

immediately without a soft start.

SR1 and SR2 immediately recover to

normal condition.

A PSON signal is needed to reenable the

PWM outputs.

Reserved.

[3:2]

Fault response

R/W

These bits specify the action when the flag is set.

Bit 3

Bit 2

Fault Response

Continues operation without interruption.

Disable SR1 and SR2.

Disable all PWM outputs.

Reserved.

[1:0]

Action after the fault

flag is cleared

R/W

These bits specify the action when the flag is cleared.

Bit 1

Bit 0

Action After Fault Flag Clears

After the flag reenable delay time, the PWM outputs are reenabled with a soft start.

The PWM outputs are reenabled immediately without a soft start.

A PSON signal, programmed in Register 0x01, Register 0x02, and/or the CTRL pin, is

needed to reenable the PWM outputs.

Reserved.

Table 113. Register 0xFE05—Flag Reenable Delay, VDD_OV_RESPONSE

Bits

Bit Name/Function

R/W

Description

[7:6]

Flag reenable delay

R/W

These bits specify the global delay from the time when a manufacturer specific flag is cleared to the

soft start.

Bit 7

Bit 6

Typical Delay Time (sec)

250 m

500 m

VDD_OV flag ignore

R/W

This bit enables or disables the VDD_OV flag.

0 = the VDD_OV flag is set when there is a VDD overvoltage condition. When there is a VDD overvoltage

condition, the flag is set and the device shuts down. When the VDD overvoltage condition ends, the

flag is cleared and the device downloads the EEPROM contents before restarting with a soft start

process.

1 = the VDD_OV flag is always cleared. When there is a VDD overvoltage condition, the flag is always

cleared and the device continues to operate without interruption.

VDD_OV flag

debounce

R/W

This bit sets the debounce time for the VDD_OV flag.

0 = 500 μs debounce time.

1 = 2 μs debounce time.

[3:0]

Reserved

R/W

Reserved.

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