ADP1052ACPZ-R7 datasheet(22/113 Pages) AD

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ADP1052

Data Sheet

Rev. B | Page 22 of 113

From the voltage sense ADC outputs to the digital compensator

output, the transfer function of the digital compensator in

z-domain is as follows:

( )

−

204

where:

d = low frequency filter gain register values (Register 0xFE30

for normal mode or Register 0xFE34 for light load mode).

m is the scale factor, as follows:

m = 1 when 49 kHz ≤ fSW < 97.5 kHz.

m = 2 when 97.5 kHz ≤ fSW < 195.5 kHz.

m = 4 when 195.5 kHz ≤ fSW < 390.5 kHz.

m = 8 when 390.5 kHz ≤ fSW.

c = high frequency filter gain register values (Register 0xFE33

for normal mode or Register 0xFE37 for light load mode).

b = high frequency filter zero register values ÷ 256

(Register 0xFE31 ÷ 256 for normal mode or Register 0xFE35 ÷

256 for light load mode).

a = high frequency filter pole register values ÷ 256

(Register 0xFE32 ÷ 256 for normal mode or Register 0xFE36 ÷

256 for light load mode).

To tailor the loop response to the specific application, set up the

low frequency gain (represented by d), the zero location of the

high frequency filter (represented by b), the pole location of the

high frequency filter (represented by a), and the high frequency

gain (represented by c). These can all be set up individually (see

the Digital Compensator and Modulation Setting Registers

section).

It is recommended that the ADP1052 GUI be used to program

the compensator. The GUI displays the filter response, using a

Bode plot in the s-domain, and calculates all stability criteria for

the power supply.

To transfer the z-domain value to the s-domain, plug the following

bilinear transformation equation into the H(z) equation:

z(s)

−

The filter introduces an extra phase delay element into the control

loop. The digital compensator circuit sends the information

about the duty cycle to the digital PWM engine at the beginning of

each switching cycle (unlike an analog controller, which makes

decisions on the duty cycle information continuously). There is an

additional delay for ADC sampling and decimation filtering. This

extra phase delay for phase margin (Φ) is expressed as follows:

Φ = 360 × fC/fSW

where fC is the crossover frequency and fSW is the switching

frequency.

At one-tenth of the switching frequency, the phase delay is 36°.

The GUI incorporates this phase delay into its calculations.

Note that the ADP1052 GUI does not account for other delays,

such as gate driver and propagation delays.

Two sets of registers allow for two distinct compensator responses.

The main compensator, called the normal mode compensator, is

controlled by programming Register 0xFE30 to Register 0xFE33.

The light load mode compensator is controlled by programming

light load mode compensator only when it operates in light load

mode or deep light load mode.

In addition, a dedicated filter is used during soft start. The filter

is disabled at the end of the soft start routine, after which time

the voltage loop digital compensator is used. The soft start filter

gain is a programmable value of 1, 2, 4, or 8, using Bits[1:0] in

CLOSED-LOOP INPUT, VOLTAGE FEEDFORWARD

CONTROL, AND VF SENSE

The ADP1052 supports closed-loop input, voltage feedforward

control to improve input transient performance. The voltage

feedforward (VF) value is sensed by the feedforward ADC and

divides the output of the digital compensator; the result is fed

into the digital PWM engine. The input voltage signal can be

sensed at the center tap in the secondary windings of the isolation

transformer and must be filtered by a residual current device

(RCD) circuit network to eliminate the voltage spike at the

switching node. Alternatively, the input voltage signal can be

sensed from a winding of the auxiliary power transformer.

The VF pin voltage (Pin 5) must be set to 1 V when the nominal

input voltage is applied. The feedforward ADC sampling period

is 10 μs. Therefore, the decision to modify the PWM outputs,

based on the input voltage, is performed at this rate.

As shown in Figure 22, the feedforward scheme modifies the

modulation value, based on the VF voltage. When the VF input

is 1 V, the line voltage feedforward has no effect. For example, if

the digital compensator output remains unchanged and the VF

voltage changes to 50% of its original value (still greater than 0.5 V),

the modulation of the edges of OUTx (that are configured for

modulation) doubles.

DIGITAL

COMPENSATOR

DPWM

ENGINE

1/x

Σ-Δ

ADC

READ_VIN

REG 0x88

REG 0x35,

REG 0x36

FEED-

FORWARD

ADC

0.5V TO 1.6V

0V TO 1.6V

VIN_LOW

FLAG REG 0x7C[3]

REG 0xFE29[5]

VIN_UV_FAULT

FLAG REG 0x7C[4]

FROM THE VIN

SENSE CIRCUIT

Figure 22. Closed-Loop Input Voltage Feedforward Configuration

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