ADP1052ACPZ-R7 datasheet(41/113 Pages) AD

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Data Sheet

ADP1052

Rev. B | Page 41 of 113

POWER SUPPLY CALIBRATION AND TRIM

Every ADP1052 device is factory trimmed. If the ADP1052 is

not trimmed in the power supply production environment, it is

recommended that components with a 0.1% tolerance be used

for the inputs to the CS1, CS2±, VS±, VF, and OVP pins to meet

data sheet specifications (see Figure 1 and the Specifications

section).

In the power supply production environment, the ADP1052 can

calibrate items, such as output voltage and trim, for tolerance

errors that are introduced by sense resistors and resistor dividers,

as well as its own internal circuitry. The ADP1052 allows the

user enough trim capability to trim for external components

with a tolerance of ≤0.5%.

To unlock the trim registers for write access, the user must

perform two consecutive write actions with the correct password

(factory default value = 0xFF), using the TRIM_PASSWORD

command (Register 0xD6). Any read or write action to another

interrupts the unlocking of the chip password.

The trim registers are Register 0xFE14 through Register 0xFE17,

see the Manufacturer Specific Extended Commands Descriptions

section.

IIN TRIM (CS1 TRIM)

Using a DC Signal

A known dc voltage (Vx) is applied at the CS1 pin. The IIN_

SCALE_MONITOR command (Register 0xD9) is set to 0x0001.

The READ_IIN input current reading command (Register 0x89)

generates a digital code (representing the input current in amperes)

that is equal to the Vx voltage value. The CS1 gain trim register

(Register 0xFE14) is adjusted until the input current reading in

Using an AC Signal

A known current (Ix) is applied to the PSU input. This current

passes through a current transformer, a diode rectifier, and an

external resistor (RCS1) to convert the current information to a

voltage (Vx). This voltage is fed into the CS1 pin. The IIN_SCALE_

MONITOR is calculated as follows:

IIN_SCALE_MONITOR = (NPRI/NSEC) × RCS1

where NPRI and NSEC are the turns of the primary side and secondary

side windings, respectively, of the current transformer.

The READ_IIN input current reading command generates a digital

code, representing the input current, Ix. The CS1 gain trim register

(Register 0xFE14) is adjusted until the input current reading in

IOUT TRIM (CS2 TRIM)

CS2 Offset Trim

Offset errors are caused by the combined mismatch of the external

level shifting resistors and the internal current sources. The level

shift resistors must have a tolerance of ≤0.1%. The offset trim has

both an analog and a digital component. With 0 V at the CS2±

inputs, the desired ADC reading is 0 LSB.

The analog offset trim is performed to achieve a differential input

voltage of 0 V. The digital offset trim is performed to achieve an

ADC reading of 0 LSB. It is important to perform the offset trim in

the following order:

1. Select high-side or low-side current sensing, using

2. Set the current sense resistor value, using the IOUT_CAL_

GAIN command (Register 0x38). It is important to note that

the real IOUT_CAL_GAIN value should be slightly greater

than the current sense resistor value, due to possible copper

trace and soldering resistance. The real IOUT_CAL_GAIN

value must be determined for accurate reading of the output

current.

3. Set the digital offset trim value to 0x00, using Register 0xFE16.

4. Adjust the CS2 analog offset trim value (Register 0xFE17)

until the value in Register 0xFEA8 reads as close as possible

to 100 decimal.

5. Increase the CS2 digital offset trim register value, using

The offset trim is then complete. With 0 V at the CS2± inputs, the

ADC code reads 0, and the READ_IOUT reading is 0 A.

CS2 Gain Trim

After completing the offset trim, perform the gain trim to remove

any mismatch that is introduced by the current sense resistor

tolerance. The ADP1052 can trim for current sense resistors

with a tolerance of ≤1%.

1. Apply a known current (IOUT) across the sense resistor.

2. Adjust the CS2 gain trim value in Register 0xFE15 until the

READ_IOUT value in Register 0x8C reads the value.

The CS2 circuit is now trimmed. After the current sense trim

is complete, the IOUT_OC_FAULT_LIMIT and IOUT_OC_

FAULT_RESPONSE are configured.

VOUT TRIM (VS TRIM)

The voltage sense (VS) input at the VS± pins is optimized for

sensing signals at 1 V and cannot sense a signal greater than

1.6 V. It is recommended that the nominal output voltage be

reduced to 1 V for best performance. The resistor divider

introduces errors that must be trimmed. The ADP1052 has

enough trim range to trim errors that are introduced by

resistors with a tolerance of ≤0.5%.

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