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ADP1052ACPZ-R7 Folha de dados(PDF) 88 Page - Analog Devices

Nome de Peças ADP1052ACPZ-R7
Descrição Electrónicos  Digital Controller for Isolated Power Supply with PMBus Interface
PDF  113 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
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ADP1052ACPZ-R7 Folha de dados(HTML) 88 Page - Analog Devices

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ADP1052
Data Sheet
Rev. B | Page 88 of 113
Bits
Bit Name/Function
R/W
Description
[3:0]
CS2 light load
threshold
R/W
These bits set the current limit on the CS2 ADC to enter the light load mode value. This value
determines the point at which the LIGHT_LOAD flag is set. The hysteresis and the averaging
speed are programmable in Register 0xFE1E[5:2].
Bit 3
Bit 2
Bit 1
Bit 0
Light Load Threshold (mV)
328 μs
164 μs
82 μs
41 μs
0
0
0
0
0
0
0
0
0
0
0
1
0.9375
1.8750
3.7500
7.5000
0
0
1
0
1.8750
3.7500
7.5000
15.000
0
0
1
1
2.8125
5.6250
11.250
22.500
0
1
0
0
3.7500
7.5000
15.000
30.000
0
1
0
1
4.6875
9.3750
18.750
37.500
0
1
1
0
5.6250
11.250
22.500
45.000
0
1
1
1
6.5625
13.125
26.250
52.500
1
0
0
0
7.5000
15.000
30.000
60.000
1
0
0
1
8.4375
16.875
33.750
67.500
1
0
1
0
9.3750
18.750
37.500
75.000
1
0
1
1
10.313
20.625
41.250
82.500
1
1
0
0
11.250
22.500
45.000
90.000
1
1
0
1
12.188
24.375
48.750
97.500
1
1
1
0
13.125
26.250
52.500
105.00
1
1
1
1
14.063
28.125
56.250
112.50
Table 131. Register 0xFE1A—IIN_OC_FAST_FAULT_LIMIT and SR_RC_FAULT_LIMIT
Bits
Bit Name/Function
R/W
Description
7
Reserved
R/W
Reserved.
[6:4]
IIN_OC_FAST_
FAULT_LIMIT
R/W
If the CS1 cycle-by-cycle current-limit comparator is set and the CS1_OCP flag is triggered, all PWM
outputs that are on at that time can be programmed to be immediately disabled for the remainder of the
switching cycle. The PWM outputs resume normal operation at the beginning of the next switching
cycle.
There is an internal counter, N, with an initial value of 0. N counts the CS1_OCP flag triggering number
in consecutive switching cycles. If the CS1_OCP flag is triggered in one cycle, then NCURRENT = NPREVIOUS + 2.
If the CS1_OCP flag is not triggered in one cycle and the previous N > 0, then NCURRENT = NPREVIOUS − 1.
If the CS1_OCP flag is not triggered and the previous N = 0, then NCURRENT = 0. When N reaches the
IIN_OC_FAST_FAULT_LIMIT value, the IIN_OC_FAST_FAULT flag is set.
Note that there is one cycle in single-ended topologies, such as buck converter and forward
converter. There are two cycles in double-ended topologies, such as full bridge converter, half bridge
converter, and push pull converter.
Bit 6
Bit 5
Bit 4
Limit Value
0
0
0
2
0
0
1
8
0
1
0
16
0
1
1
64
1
0
0
128
1
0
1
256
1
1
0
512
1
1
1
1024
3
SR_RC_FAULT flag
debounce time
R/W
This bit sets the debounce time for the SR_RC_FAULT flag.
0 = 40 ns.
1 = 200 ns.



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