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ADP1052

Data Sheet

Rev. B | Page 48 of 113

Clock Generation and Stretching

The ADP1052 is always a PMBus slave device in the overall system;

therefore, the device never needs to generate the clock, which is

done by the master device in the system. However, the PMBus

slave device is capable of clock stretching to force the master into

a wait state. By stretching the SCL signal during the low period, the

slave device communicates to the master device that it is not

ready and the master device must wait.

Conditions in which the PMBus slave device stretches the SCL

line low include the following:

•

The master device is transmitting at a higher baud rate

than the slave device.

•

The receive buffer of the slave device is full and must be

read before continuing. This prevents a data overflow

condition.

•

The slave device is not ready to send data that the master

has requested.

Note that the PMBus slave device can stretch the SCL line during

the low period only. Also, whereas the I2C specification allows

indefinite stretching of the SCL line, the PMBus specification

limits the maximum time that the SCL line can be stretched, or

held low, to 25 ms. After this time period, the slave device must

release the communication lines and reset its state machine.

Start and Stop Conditions

Start and stop conditions involve serial data transitions when the

serial clock is at a logic high level. The PMBus slave device moni-

tors the SDA and SCL lines to detect the start and stop conditions

and transition its internal state machine accordingly. Typical

start and stop conditions are shown in Figure 54.

SCL

SDA

START

STOP

Figure 54. Start and Stop Transitions

GENERAL CALL SUPPORT

The PMBus slave is capable of decoding and acknowledging a

general call address. The PMBus slave device responds to both

its own address and the general call address (0x00). The general

call address enables all devices on the PMBus to be written to

simultaneously.

Note that all PMBus commands must start with a slave address,

with the R/W bit cleared to 0 and followed by the command code.

This is also true when using the general call address to communi-

cate with the PMBus slave device.

10-BIT ADDRESSING

The ADP1052 does not support 10-bit addressing as defined in

the I2C specification.

FAST MODE

Fast mode, with a data rate of 400 kbps, uses essentially the

same mechanics as the standard mode of operation; the electrical

specifications and timing are most affected. The PMBus slave is

capable of communicating with a master device operating in fast

mode or in standard mode, which has a data rate of 100 kbps.

FAULT CONDITIONS

The PMBus protocol provides a comprehensive set of fault

conditions that must be monitored and reported. These fault

conditions can be grouped into two major categories: communi-

cation faults and monitoring faults.

Communication faults are error conditions associated with the

data transfer mechanism of the PMBus protocol. Monitoring

faults are error conditions associated with the operation of the

ADP1052, such as output overvoltage protection. These fault

conditions are described in detail in the Power Monitoring,

Flags, and Fault Responses section.

TIMEOUT CONDITIONS

The SMBus specification includes three clock stretching

specifications related to timeout conditions.

A timeout condition occurs if any single SCL clock pulse is held

low for longer than the minimum tTIMEOUT value of 25 ms. Upon

detecting the timeout condition, the PMBus slave device has 10 ms

to abort the transfer, release the bus lines, and be ready to accept

a new start condition. The device initiating the timeout is required

to hold the SCL clock line low for at least the maximum tTIMEOUT

value of 35 ms, guaranteeing that the slave device is given enough

time to reset its communication protocol.

DATA TRANSMISSION FAULTS

Data transmission faults occur when two communicating devices

violate the PMBus communication protocol, as specified in the

PMBus specification. See the PMBus specification for more

information about each fault condition.

Corrupted Data, Packet Error Checking (PEC)

Packet error checking is not supported by the ADP1052.

Sending Too Few Bits

Transmission is interrupted by a start or stop condition before a

complete byte (eight bits) has been sent. This function is not

supported; any transmitted data is ignored.

Reading Too Few Bits

Transmission is interrupted by a start or stop condition before a

complete byte (eight bits) has been read. This function is not

supported; any received data is ignored.

Host Sends or Reads Too Few Bytes

If a host ends a packet with a stop condition before the required

bytes are sent/received, it is assumed that the host intended to

stop the transfer. Therefore, the PMBus does not consider this

to be an error and takes no action, except to flush any remaining

bytes in the transmit FIFO.

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