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ADP1052ACPZ-R7 Folha de dados(PDF) 7 Page - Analog Devices |
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ADP1052ACPZ-R7 Folha de dados(HTML) 7 Page - Analog Devices |
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7 / 113 page  Data Sheet ADP1052 Rev. B | Page 7 of 113 Parameter Symbol Min Typ Max Unit Test Conditions/Comments RTD ADC Valid Input Voltage Range 0 1.6 V ADC Clock Frequency 1.56 MHz Register Update Rate 10 ms Measurement Resolution 12 Bits Accuracy −0.3 +0.45 % FSR 2% to 20% of the input voltage range −4.8 +7.2 mV −2 +2 % FSR 0% to 100% of the input voltage range −80 +80 mV OTP Digital Comparator Triggers OT_FAULT flag Threshold Accuracy −0.9 +0.25 % FSR T = 85°C with 100 kΩ||16.5 kΩ −14.4 +4 mV −0.5 +1.1 % FSR T = 100°C with 100 kΩ||16.5 kΩ −8 +17.6 mV Comparator Update Speed 10 ms Temperature Readings According to Internal Linearization Scheme Current source set to 46 µA (Register 0xFE2D = 0xE6); NTC R25 = 100 kΩ (1%); beta = 4250 (1%); REXT = 16.5 kΩ (1%) 7 °C 25°C to 100°C 5 °C 100°C to 125°C PG/ALT (OPEN-DRAIN) PIN Output Low Level VOL 0.4 V Sink current = 10 mA CTRL PIN Input Level Low VIL 0.4 V High VIH VDD − 0.8 V Leakage Current 1.0 µA SYNI/FLGI PINS Input Level Low VIL 0.4 V High VIH VDD − 0.8 V Synchronization Range, Percent of Internal Clock Period tSYNC 90 110 % SYNI Pulse Width Positive 360 ns External clock applied on the SYNI/FLGI pin Negative 360 ns External clock applied on the SYNI/FLGI pin SYNI Period Drift 280 ns Period drift between two consecutive external clocks Leakage Current 1.0 µA SDA, SCL PINS Input Voltage Low VIL 0.8 V High VIH VDD − 0.8 V Output Voltage Low VOL 0.4 V Sink current = 3 mA Leakage Current −5 +5 µA SERIAL BUS TIMING See Figure 2 Clock Operating Frequency 10 100 400 kHz Glitch Immunity 50 ns Bus Free Time tBUF 1.3 µs Between stop and start conditions |
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