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Data Sheet

ADP1052

Rev. B | Page 27 of 113

DEBOUNCE

VIN_UV_FAULT

IIN_OC_FAST_FAULT

DEBOUNCE

REG 0xFE0D

REG 0xFE0F

REG 0xFE0E[3:0]

DEBOUNCE

PGOOD FLAG

REG 0xFEA0[6]

PG/ALT PIN

IOUT_OC_FAULT

VOUT_OV_FAULT

VOUT_UV_FAULT

OT_FAULT

OT_WARNING

SR_RC_FAULT

POWER_OFF

SOFT_START_FILTER

CRC_FAULT

POWER_GOOD

Figure 30. PGOOD Programming

The POWER_GOOD_ON command (Register 0x5E) sets

the voltage limit that the output voltage must exceed before

the POWER_GOOD flag (Register 0x79[11]) can be cleared.

Similarly, the output voltage must fall below the POWER_GOOD_

OFF limit (Register 0x5F) to set the POWER_GOOD flag.

The PG/ALT pin is always driven low and the PGOOD flag is

always set when one of the POWER_OFF, SOFT_START_FILTER,

CRC_FAULT, or POWER_GOOD flags is set.

The debounce timings for setting and clearing the PGOOD

flag can be programmed to 0 ms, 200 ms, 320 ms, or 600 ms in

VOLT-SECOND BALANCE CONTROL

The ADP1052 has a dedicated circuit to maintain volt-second

balance in the main transformer when operating in full bridge

topology. This circuit eliminates the need for a dc blocking

capacitor. In interleaved topologies, volt-second balance can also

be used for current balancing to ensure that each interleaved

phase contributes equal power.

The circuit monitors the current flowing in both legs of the full

bridge topology and stores this information. It compensates the

selected PWM signals to ensure equal current flow in the two legs

of the full bridge topology. The CS1 pin is the input for this

function.

Several switching cycles are required for the circuit to operate

effectively. The maximum amount of modulation applied to each

edge of the selected PWM outputs is programmable to ±80 ns

or ±160 ns, using Register 0xFE54[2]. The balance control gains

are programmable via Register 0xFE54[1:0].

The compensation of the PWM drive signals is performed on

the edges of two selected outputs, using Register 0xFE55,

modulation is also programmable in these registers.

The volt-second balance control can be disabled during soft start

with Register 0xFE0C[1].

There are also leading edge blanking functions at the sensed CS1

signal for more accurate control results. The blanking time follows

the CS1 cycle-by-cycle current-limit blanking time (see the

Current Sense section).

To avoid the wrong compensation in light load mode, the CS1

threshold in Register 0xFE38 enables the volt-second balance.

Below this threshold, volt-second balance is not enabled.

CONSTANT CURRENT MODE

Constant current mode is part of the PMBus output current

fault response function. When the output current reaches the

IOUT_OC_FAULT_LIMIT value, the ADP1052 can be config-

ured to operate in constant current mode, using the output

current as the feedback signal for closed-loop operation (see

Figure 31). To ensure that the output current remains constant, the

output voltage is ramped down linearly as the load resistance

decreases.

VOUT

IOUT

IOUT_OC_FAULT_LIMIT

(REG 0x46)

VOUT NOMINAL

IOUT NOMINAL

Figure 31. Constant Current Mode (VOUT vs. IOUT)

Two CS2 output current averaging speeds can be selected via

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