RA4L1 datasheet(106/125 Pages) RENESAS

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C3: A capacitor connected between VL2 and GND

C4: A capacitor connected between VL4 and GND

C1 = C2 = C3 = C4 = 0.47 µF ±30%

Note 3. Bit [7] (MDSET[2]) of register VLCD is set to 1 and bits [7:6] (MDSET[1:0]) of register LCDM0 are set to 10 for capacitor split

method (VL4 reference).

2.13

Flash Memory Characteristics

2.13.1

Code Flash Memory Characteristics

Table 2.75

Code flash characteristics (1)

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

Reprogramming/erasure cycle*1

NPEC

1000

—

Times

—

Data hold time After 1000 times NPEC

tDRP

20*2 *3

—

Year

Ta = +105 °C

—

Year

Ta = +125 °C

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 1,000),

erasing can be performed n times for each block. For instance, when 8-byte programming is performed 256 times for different

addresses in 2-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming

the same address for several times as one erasure is not enabled (overwriting is prohibited).

Note 2. Characteristic when using the flash memory programmer and the self-programming library provided by Renesas Electronics.

Note 3. This result is obtained from reliability testing.

Table 2.76

Code flash characteristics (2)

High-speed operating mode

Conditions: VCC = AVCC0 = 1.8 to 3.6 V

Parameter

Symbol

ICLK = 1 MHz

ICLK = 48 MHz

Unit

Min

Typ

Max

Min

Typ

Max

Programming time

8-byte

tP8

—

128

1064

—

44.2

420

µs

Erasure time

2-KB

tE2K

—

14.1

390

—

5.5

214

Blank check time

8-byte

tBC8

—

67.7

—

8.6

µs

2-KB

tBC2K

—

7538

—

272

µs

Erase suspended time

tSED

—

33.4

—

10.7

µs

Forced stop time

tFD

—

33.4

—

10.7

µs

Configuration Set time

tCFGS

—

494

—

255

Flash memory mode transition wait

time 1

tDIS

—

µs

Flash memory mode transition wait

time 2

tMS

—

µs

Note:

Does not include the time until each operation of the flash memory is started after instructions are executed by software.

Note:

The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory.

Note:

The frequency accuracy of FCLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy

of the clock source.

Table 2.77

Code flash characteristics (3) (1 of 2)

Middle-speed operating mode

Conditions: VCC = AVCC0 = 1.6 to 3.6 V

Parameter

Symbol

ICLK = 1 MHz

ICLK = 8 MHz*1

Unit

Min

Typ

Max

Min

Typ

Max

Programming time

8-byte

tP8

—

128

1064

—

50.6

468

µs

Erasure time

2-KB

tE2K

—

14.1

390

—

6.32

231

Blank check time

8-byte

tBC8

—

67.7

—

13.3

µs

2-KB

tBC2K

—

7538

—

947

µs

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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