RA4L1 datasheet(62/125 Pages) RENESAS

62 / 125 page

Table 2.39

SPI timing (2 of 3)

Parameter

Symbol

Min

Max

Unit

Test conditions

Data input setup

time

Master

2.7 V ≤ VCC ≤ 3.6 V

tSU

—

Figure 2.32 to

Figure 2.37

C = 30 pF

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Slave

2.4 V ≤ VCC ≤ 3.6 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Data input hold

time

Master (RSPCK is PCLKA/2)

tHF

—

Master (RSPCK is not PCLKA/2)

tPcyc

—

Slave

—

SSL setup time

Master

1.8 V ≤ VCC ≤ 3.6 V

tLEAD

−30 + N × tSpcyc*1

—

1.6 V ≤ VCC < 1.8 V

−50 + N × tSpcyc*1

—

Slave

6 × tPcyc

—

SSL hold time

Master

tLAG

−30 + N × tSpcyc*2

—

Slave

6 × tPcyc

—

Data output

delay time

Master

2.7 V ≤ VCC ≤ 3.6 V

tOD

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Slave

2.7 V ≤ VCC ≤ 3.6 V

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Data output hold

time

Master

tOH

—

Slave

—

Successive

transmission

delay time

Master

tTD

tSPcyc + 2 × tPcyc

8 × tSPcyc + 2 ×

tPcyc

Slave

4 × tSPcyc

—

MOSI and MISO

rise and fall time

Output

2.7 V ≤ VCC ≤ 3.6 V

tDr, tDf

—

Figure 2.32 to

Figure 2.37

C = 30 pF

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Input

—

SSL rise and fall

time

Output

2.7 V ≤ VCC ≤ 3.6 V

tSSLr,

tSSLf

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Input

—

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 62 of 125

RA4L1 Folha de dados(PDF) 62 Page - Renesas Technology Corp

RA4L1 Folha de dados(HTML) 62 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL