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tSU

tLEAD

tTD

tLAG

tOH

tOD

MSB IN

DATA

LSB IN

MSB OUT

DATA

LSB OUT

IDLE

QSSL

output

QSPCLK

output

QIO0-3

input

QIO0-3

output

Figure 2.39

Transmit and receive timing

2.3.11

IIC Timing

Table 2.41

IIC timing (1) (1 of 2)

Conditions: VCC = AVCC0 = 1.8 to 3.6 V

Parameter

Symbol

Min*1

Max*1

Unit Test conditions

IIC (standard mode,

SMBus)

ICFER.FMPE = 0

SCL input cycle time

tSCL

6 (12) × tIICcyc + 1300

—

Figure 2.40

SCL input high pulse width

tSCLH

3 (6) × tIICcyc + 300

—

SCL input low pulse width

tSCLL

3 (6) × tIICcyc + 300

—

SCL, SDA rise time

tSr

—

1000

SCL, SDA fall time

tSf

—

300

SCL, SDA input spike pulse

removal time

tSP

1 (4) × tIICcyc

SDA input bus free time when

wakeup function is disabled

tBUF

3 (6) × tIICcyc + 300

—

SDA input bus free time when

wakeup function is enabled

tBUF

3 (6) × tIICcyc + 4 ×

tPcyc + 300

—

START condition input hold time

when wakeup function is disabled

tSTAH

tIICcyc + 300

—

START condition input hold time

when wakeup function is enabled

tSTAH

1 (5) × tIICcyc + tPcyc +

300

—

Repeated START condition input

setup time

tSTAS

1000

—

STOP condition input setup time

tSTOS

1000

—

Data input setup time

tSDAS

tIICcyc + 50

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*2

—

400

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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