RA4L1 datasheet(102/125 Pages) RENESAS

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2.12.2

Internal Voltage Boosting Method (VL1 Reference)

(1) 1/3 bias method

Table 2.70

Internal voltage boosting method LCD characteristics (1)

Conditions: VCC = AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0 V

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Test conditions

LCD output voltage

variation range

VL1

C1 to C4*5 = 0.47

µF

VLCD*1 = 0x04

0.97

1.01

1.04

—

VLCD = 0x05

1.00

1.04

1.08

—

VLCD = 0x06

1.04

1.07

1.11

—

VLCD = 0x07

1.07

1.11

1.14

—

VLCD = 0x08

1.10

1.14

1.18

—

VLCD = 0x09

1.13

1.17

1.21

VLCD = 0x0A

1.16

1.21

1.25

—

VLCD = 0x0B

1.20

1.24

1.28

—

VLCD = 0x0C

1.23

1.27

1.32

—

VLCD = 0x0D

1.26

1.31

1.35

—

VLCD = 0x0E

1.29

1.34

1.38

—

VLCD = 0x0F

1.33

1.37

1.42

VLCD = 0x10

1.36

1.40

1.45

—

VLCD = 0x11

1.39

1.44

1.49

—

VLCD = 0x12

1.42

1.47

1.52

—

VLCD = 0x13

1.45

1.50

1.55

—

VLCD = 0x14

1.49

1.54

1.59

—

VLCD = 0x15

1.52

1.57

1.62

VLCD = 0x16

1.55

1.60

1.66

—

VLCD = 0x17

1.58

1.64

1.69

—

VLCD = 0x18

1.61

1.67

1.73

—

VLCD = 0x19

1.65

1.70

1.76

—

VLCD = 0x1A*4

1.68

1.74

1.79

—

Double output

voltage

VL2

C1 to C4*5 = 0.47 µF

2 × VL1 -

2 × VL1

+ 5%

—

Triple output

voltage

VL4

C1 to C4*5 = 0.47 µF

3 × VL1 -

3 × VL1

+ 6%

—

Reference voltage

setup time*2

tVL1S

—

Figure 2.71

Voltage boost wait

time*3

tVLWT

—

500

—

Figure 2.71

Note:

0x0E to 0x1A setting is permitted when using 5V LCD panel, 0x04 to 0x07 setting is permitted when using 3V LCD panel at 1/3

bias.

Note 1. Bit [7] (MDSET[2]) of register VLCD is set to 0 and bits [7:6] (MDSET[1:0]) of register LCDM0 are set to 01 for internal voltage

boosting method (VL1 reference), and bits [4:0] (VLCD4-0) of register VLCD are used for voltage variation setting.

Note 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal

voltage boosting method is selected (by setting the MDSET[1:0] bits of the LCDM0 register to 01b and MDSET[2] of the register

VLCD to 0) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1).

Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).

Note 4. This setting is only available when VCC ≥ VL1.

Note 5. This is a capacitor that is connected between the voltage pins that are used to drive the LCD.

C1: A capacitor connected between CAPH and CAPL

C2: A capacitor connected between VL1 and GND

C3: A capacitor connected between VL2 and GND

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 102 of 125

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