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2.3.8

SCI Timing

Table 2.36

SCI timing (1) (1 of 2)

Conditions: VCC = AVCC0 = 1.6 to 3.6 V

Parameter

Symbol

Min

Max

Unit

Test

conditions

SCI

Input clock cycle

Asynchronous

2.7 V ≤ VCC ≤ 3.6 V

tScyc

—

Figure 2.23

2.4 V ≤ VCC < 2.7 V

150

—

1.8 V ≤ VCC < 2.4 V

300

—

1.6 V ≤ VCC < 1.8 V

1000

—

Clock

synchronous

2.7 V ≤ VCC ≤ 3.6 V

100

—

2.4 V ≤ VCC < 2.7 V

200

—

1.8 V ≤ VCC < 2.4 V

400

—

1.6 V ≤ VCC < 1.8 V

1500

—

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Input clock rise time

tSCKr

—

Input clock fall time

tSCKf

—

Output clock cycle

Asynchronous

2.7 V ≤ VCC ≤ 3.6 V

tScyc

75 (exclude SCI1)

100 (SCI1)

—

2.4 V ≤ VCC < 2.7 V

150 (exclude SCI1)

200 (SCI1)

—

1.8 V ≤ VCC < 2.4 V

300 (exclude SCI1)

400 (SCI1)

—

1.6 V ≤ VCC < 1.8 V

1500 (exclude SCI1)

2000 (SCI1)

—

Clock

synchronous

1.8 V ≤ VCC ≤ 3.6 V

—

2.4 V ≤ VCC < 2.7 V

150

—

1.8 V ≤ VCC < 2.4 V

300

—

1.6 V ≤ VCC < 1.8 V

1000

—

Output clock pulse width

tSCKW

0.4

0.6

tScyc

Output clock rise time

1.8 V ≤ VCC ≤ 3.6 V

tSCKr

—

7.5

1.6 V ≤ VCC < 1.8 V

—

Output clock fall time

1.8 V ≤ VCC ≤ 3.6 V

tSCKf

—

7.5

1.6 V ≤ VCC < 1.8 V

—

Transmit data

delay time

(master)

Clock

synchronous

2.7 V ≤ VCC ≤ 3.6 V

tTXD

—

Figure 2.24

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

125

Transmit data

delay time (slave)

Clock

synchronous

1.8 V ≤ VCC ≤ 3.6 V

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

105

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 55 of 125

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