RA4L1 datasheet(63/125 Pages) RENESAS

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Table 2.39

SPI timing (3 of 3)

Parameter

Symbol

Min

Max

Unit

Test conditions

Slave access time

2.7 V ≤ VCC ≤ 3.6 V

tSA

—

2 × tPcyc + 11

Figure 2.36 and

Figure 2.37

C = 30 pF

2.4 V ≤ VCC < 2.7 V

—

2 × tPcyc + 15

1.8 V ≤ VCC < 2.4 V

—

2 × tPcyc + 35

1.6 V ≤ VCC < 1.8 V

—

2 × tPcyc + 55

Slave output release time

2.7 V ≤ VCC ≤ 3.6 V

tREL

—

2 × tPcyc + 11

2.4 V ≤ VCC < 2.7 V

—

2 × tPcyc + 15

1.8 V ≤ VCC < 2.4 V

—

2 × tPcyc + 35

1.6 V ≤ VCC < 1.8 V

—

2 × tPcyc + 55

Note:

tPcyc: PCLKA cycle.

Note 1. N is set as an integer from 1 to 8 by the SPCKD register.

Note 2. N is set as an integer from 1 to 8 by the SSLND register.

RSPCKn

master select

output

RSPCKn

slave select input

tSPCKWH

VOH

VOL

VOH

tSPCKWL

tSPCKr

tSPCKf

VOL

tSPcyc

tSPCKWH

VIH

VIL

VIH

tSPCKWL

tSPCKr

tSPCKf

VIL

tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

Note:

n = A or B

Figure 2.31

SPI clock timing

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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