RA4L1 datasheet(35/125 Pages) RENESAS

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Note 1. Except for Ports P200, P214, and P215, which are input ports.

Table 2.9

I/O other characteristics

Conditions: VCC = AVCC0 = 1.6 to 3.6 V

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Input leakage current

RES, ports P200, P214, P215

| Iin |

—

1.0

µA

Vin = 0 V

Vin = VCC

Three-state leakage

current (off state)

5V-tolerant ports*1

| ITSI |

—

1.0

µA

Vin = 0 V

Vin = 5.8 V

Other ports (except for P200,

P214, P215, and 5V-tolerant ports)

—

1.0

Vin = 0 V

Vin = VCC

Input pull-up resistor

All ports (except for P200, P214,

P215)

100

kΩ

Vin = 0 V

Input capacitance

P200

Cin

—

Vin = 0 V,

f = 1 MHz

Ta = 25 °C

Other input pins

—

Note 1. P301, P302, P400, P401, and P407 (total 5 pins)

2.2.5

Operating and Standby Current

Table 2.10

High-speed mode current

Parameter

Symbol

Typ

Max

Unit

Test Conditions

Maximum*1 *2

ICC*3

—

ICLK = 80 MHz

PCLKA = 80 MHz

PCLKB = 40 MHz

PCLKC = 40 MHz

PCLKD = 80 MHz

FCLK = 40 MHz

CoreMark®*4 *5

20.4

—

255

—

uA/MHz

Normal mode

All peripheral clocks enabled, and cache

disable. While (1) code is executing from

flash*5

30.7

—

384

—

uA/MHz

All peripheral clocks disabled, and cache

disable. While (1) code is executing from

flash*4 *5

13.4

—

168

—

uA/MHz

Sleep mode

All peripheral clocks enabled, and cache

disable*5

22.8

—

All peripheral clocks disabled, and cache

disable.*4 *5

5.63

—

Increase during BGO operation*6

2.74

Note:

Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note:

This does not include the BGO operation.

Note 1. Measured with clocks supplied to the peripheral functions.

Note 2. PLL output frequency = 80MHz. The clock source is MOSC.

Note 3. ICC depends on f (ICLK) as follows (reference data).

ICC Max. = 0.80 × f + 9.51 (max. operation)

ICC Typ. = 0.15 × f + 2.37 (normal operation, all peripheral clocks disabled and cache disabled)

ICC Typ. = 0.26 × f + 3.39 (sleep mode, all peripheral clocks enabled and cache disabled)

Note 4. PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (1.25 MHz).

Note 5. PLL is stopped, and HOCO output frequency = 80 MHz

Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution.

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 35 of 125

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