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RA4L1 Folha de dados(PDF) 7 Page - Renesas Technology Corp |
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RA4L1 Folha de dados(HTML) 7 Page - Renesas Technology Corp |
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7 / 125 page ![]() 1.2 Block Diagram Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the features. Memory 512 KB code flash 8 KB data flash 64 KB SRAM DMA DMAC × 8 System Mode control Power control Register write protection MOSC/SOSC Clocks (H/M/L) OCO PLL GPT32 x 2 GPT16 x 4 Timers AGT × 2 RTC CTSU Arm Cortex-M33 DTC CAC POR/LVD Reset Human machine interfaces ELC Event link RSIP-E11A Security Analog CRC Data processing DOC Communication interfaces QSPI IIC I3C SPI CANFD SSIE USBFS SCI × 6 (IrDA × 1) TSN DAC12 ADC12 Bus MPU ICU WDT/IWDT MPU NVIC System timer DBG interface IDAU DSP FPU SLCDC UARTA × 2 ACMPLP × 2 Note: Not available on all part numbers. Figure 1.1 Block diagram 1.3 Part Numbering Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.14 shows a list of products. RA4L1 Datasheet 1. Overview R01DS0447EJ0131 Rev.1.31 May 26, 2026 Page 7 of 125 |
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