RA4L1 datasheet(57/125 Pages) RENESAS

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Table 2.37

SCI timing (2) (1 of 2)

Conditions: VCC = AVCC0 = 1.6 to 3.6 V

Parameter

Symbol

Min

Max

Unit

Test conditions

Simple

SPI

SCK clock cycle output

(master)

1.8 V ≤ VCC ≤ 3.6 V

tSPcyc

—

Figure 2.25

2.4 V ≤ VCC < 2.7 V

150

—

1.8 V ≤ VCC < 2.4 V

300

—

1.6 V ≤ VCC < 1.8 V

1000

—

SCK clock cycle input (slave)

1.8 V ≤ VCC ≤ 3.6 V

100

—

2.4 V ≤ VCC < 2.7 V

200

—

1.8 V ≤ VCC < 2.4 V

400

—

1.6 V ≤ VCC < 1.8 V

1500

—

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise and fall time

tSPCKr,

tSPCKf

—

Data input setup

time

Master

2.7 V ≤ VCC ≤ 3.6 V

tSU

—

Figure 2.26 to

Figure 2.29

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

110

—

Slave

1.8 V ≤ VCC ≤ 3.6 V

—

1.6 V ≤ VCC < 1.8 V

—

Data input hold

time

Master

—

Slave

—

SS input setup time

tLEAD

—

tSPcyc

SS input hold time

tLAG

—

tSPcyc

Data output delay

time

Master

2.4 V ≤ VCC ≤ 3.6 V

tOD

—

2.4 V ≤ VCC ≤ 2.7 V

—

1.8 V ≤ VCC ≤ 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

125

Slave

2.7 V ≤ VCC ≤ 3.6 V

—

2.4 V ≤ VCC ≤ 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

100

Data output hold

time

Master

2.7 V ≤ VCC ≤ 3.6 V

tOH

-5

—

2.4 V ≤ VCC < 2.7 V

-10

—

1.8 V ≤ VCC < 2.4 V

-20

—

1.6 V ≤ VCC < 1.8 V

-40

—

Slave

-5

—

Data rise and fall

time

Master

1.8 V ≤ VCC ≤ 3.6 V

tDr, tDf

—

Slave

1.8 V ≤ VCC ≤ 3.6 V

—

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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