RA4L1 datasheet(51/125 Pages) RENESAS

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Table 2.32

Timing of recovery from low power modes (5)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Recovery time from Software

Standby mode*1

High-speed mode System clock

source is HOCO (32 MHz)*1

tSNZ

—

7.4

9.3

μs

Figure 2.15

Middle-speed mode System clock

source is HOCO (24 MHz)*2

VCC = 1.8 V to 3.6 V

tSNZ

—

8.3

10.4

μs

Middle-speed mode System clock

source is HOCO (24 MHz)*3

VCC = 1.6 V to 1.8 V

tSNZ

—

9.5

11.8

μs

Low-speed mode System clock

source is MOCO (8 MHz)*4

tSNZ

—

11.8

15.6

μs

Note 1. The ICLK is 32 MHz

Note 2. The ICLK is 8 MHz (24 MHz/4)

Note 3. The ICLK is 4 MHz (24 MHz/8)

Note 4. The ICLK is 1 MHz (8 MHz/8)

tSNZ

IRQ

ICLK (to DTC, SRAM)*1 PCLK

ICLK (except DTC, SRAM)

Oscillator

Software Standby mode

Snooze mode

Note 1. When SNZCR.SNZDTCEN bit is set to 1, ICLK is supplied to DTC and SRAM.

Figure 2.15

Recovery timing from Software Standby mode to Snooze mode

2.3.5

NMI and IRQ Noise Filter

Table 2.33

NMI and IRQ noise filter

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

NMI pulse

width

tNMIW

200

—

NMI digital filter disabled

tPcyc × 2 ≤ 200 ns

tPcyc × 2*1

—

tPcyc × 2 > 200 ns

200

—

NMI digital filter enabled

tNMICK × 3 ≤ 200 ns

tNMICK ×

3.5*2

—

tNMICK × 3 > 200 ns

IRQ pulse

width

tIRQW

200

—

IRQ digital filter disabled

tPcyc × 2 ≤ 200 ns

tPcyc × 2*1

—

tPcyc × 2 > 200 ns

200

—

IRQ digital filter enabled

tIRQCK × 3 ≤ 200 ns

tIRQCK ×

3.5*3

—

tIRQCK × 3 > 200 ns

Note:

200 ns minimum in Software Standby mode.

Note:

If the clock source is being switched it is needed to add 4 clock cycle of switched source.

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 51 of 125

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