RA4L1 datasheet(74/125 Pages) RENESAS

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I3C_SDA0

I3C_SCL0

tSfDA

tSrDA

tSTAS

tSDAH

tSDAS

tSTOS

tSfCL

tSCLH

tSCLL

tSrCL

0.3 × VCC

= MCS current source pull-up

= Rp resistor pull-up

0.7 × VCC

0.3 × VCC

0.7 × VCC

Figure 2.42

I2C bus interface input/output timing (Hs-mode)

Table 2.46

I3C timing (open drain timing parameters)

Conditions: VCC = 3.0 to 3.60 V

Parameter

Symbol

Min

Max

Unit

Test

conditions

I3C Open Drain

Timing

Parameters

SCL Clock Low Period

tLOW_OD

*1 *2

200

—

Figure 2.45

tDIG_OD_L tLOW_ODmin + tfDA_ODmin —

Figure 2.45

SCL Clock High Period

tHIGH*3 *4 —

Figure 2.43

tDIG_H

—

tHIGH + tCF

Figure 2.43

SDA Signal Fall Time

tfDA_OD

tCF

Figure 2.45

SDA Data Setup Time Open

Drain Mode

tSU_OD*1

—

Figure 2.44

Clock After START (S) Condition tCAS*5 *6 38.4 nano

ENAS0: 1 µ

seconds

Figure 2.45

ENAS1: 100 µ

ENAS2: 2 milli

ENAS3: 50 milli

Clock Before STOP (P)

Condition

tCBP

tCASmin / 2

—

seconds

Figure 2.46

Current Master to Secondary

Master Overlap time during

handoff

tMMOverla

tDIG_OD_Lmin

—

Figure 2.51

Bus Available Condition

tAVAL*7

—

µs

—

Bus Idle Condition

tIDLE

—

Time Internal Where New

Master Not Driving SDA Low

tMMLock

tAVALmin

—

µs

Figure 2.51

Note 1. This is approximately equal to tLOWmin + tDS_ODmin + trDA_ODtyp + tSU_Odmin.

Note 2. The Master may use a shorter Low period if it knows that this is safe, i.e., that SDA is already above VIH.

Note 3. Based on tSPIKE, rise and fall times, and interconnect

Note 4. This maximum High period may be exceeded when the signals can be safely seen by Legacy I2C Devices, and/or in consideration

of the interconnect (e.g., a short Bus).

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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