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Table 2.48

SSIE timing (2 of 2)

(1) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface, the

AC portion of the electrical characteristics is measured for each group.

Parameter

Symbol

Target

specification

Unit

Test

conditions

Min

Max

SSILRCK0/

SSIFS0,

SSITXD0,

SSIRXD0

Input set up time

Master

2.7v ≤ VCC ≤ 3.6

tSR

—

Figure 2.54,

Figure 2.55

2.4 ≤ VCC < 2.7

—

1.8 ≤ VCC < 2.4

—

1.6 ≤ VCC < 1.8

—

Slave

2.7v ≤ VCC ≤ 3.6

—

1.8 ≤ VCC < 2.7

—

1.8 ≤ VCC < 2.7

—

1.6 ≤ VCC < 1.8

—

Input hold time

Master

tHR

—

Slave

—

Output delay time

Master

2.7v ≤ VCC ≤ 3.6

tDTR

2.4 ≤ VCC < 2.7

1.8 ≤ VCC < 2.4

1.6 ≤ VCC < 1.8

Slave

2.7v ≤ VCC ≤ 3.6

2.4 ≤ VCC < 2.7

1.8 ≤ VCC < 2.4

1.6 ≤ VCC < 1.8

Output delay time

from SSILRCK0/

SSIFS0 change

Slave

2.7v ≤ VCC ≤ 3.6

tDTRW

Figure 2.55,

Figure 2.56*1

2.4 ≤ VCC < 2.7

1.8 ≤ VCC < 2.4

1.6 ≤ VCC < 1.8

GTIOC2A,

AUDIO_CLK

Cycle

1.8 ≤ VCC < 3.6

tEXcyc

—

Figure 2.53

1.6 ≤ VCC < 1.8

250

—

High level/ Low level

tEXL/tEXH 0.4

0.6

tEXcyc

Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK0/SSIFS0 pin is used to generate

transmit data, and the transmit data is logically output to the SSITXD0 pin.

SSIBCK0

tHC

tO, tI

tLC

tRC

tFC

Figure 2.52

SSIE clock input/output timing

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 82 of 125

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