RA4L1 datasheet(73/125 Pages) RENESAS

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Table 2.45

IIC timing (HS-mode)

Conditions: VCC = 2.7 to 3.60 V

Parameter

Symbol

Min*1

Max*1

Unit

IIC (Hs-mode)

BFCTL.HSME = 1

SCL input cycle time

tSCL

55(57) × tI3Ccyc

—

SCL input high pulse

width

Cb = 400 pF

tSCLH

43(44) × tI3Ccyc

—

Cb = 100 pF

23(24) × tI3Ccyc

—

SCL input low pulse

width

Cb = 400 pF

tSCLL

64(65) × tI3Ccyc

—

Cb = 100 pF

32(33) × tI3Ccyc

—

SCL rise time

Cb = 400 pF

tSrCL

—

Cb = 100 pF

—

SDA rise time

Cb = 400 pF

tSrDA

—

160

Cb = 100 pF

—

SCL fall time

Cb = 400 pF

tSfCL

—

Cb = 100 pF

—

SDA fall time

Cb = 400 pF

tSfDA

—

160

Cb = 100 pF

—

SCL, SDA input spike pulse removal time tSP

1(1) × tI3Ccyc

Repeated START condition input setup

time

tSTAS

—

STOP condition input setup time

tSTOS

—

Data input setup time

tSDAS

—

Data input hold time

Cb = 400 pF

tSDAH

150

Cb = 100 pF

SCL, SDA capacitive load

Cb*2

—

400

Note:

tI3Ccyc: I3C internal reference clock (I3Cφ) cycle.

Note 1. Values in parentheses apply when INCTL.DNFS[3:0] is set to 0x3 while the digital filter is enabled with INCTL.DNFE set to 1.

Note 2. Cb indicates the total capacity of the bus line.

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 73 of 125

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