RA4L1 datasheet(103/125 Pages) RENESAS

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C4: A capacitor connected between VL4 and GND

C1 = C2 = C3 = C4 = 0.47 µF ±30%

(2) 1/4 bias method

Table 2.71

Internal voltage boosting method LCD characteristics (2)

Conditions: VCC = AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0 V

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Test

conditio

LCD output voltage variation

range

VL1

C1 to C5*1 = 0.47

µF

VLCD*2 = 0x04

0.97

1.01

1.04

—

VLCD = 0x05

1.00

1.04

1.08

—

VLCD = 0x06

1.04

1.07

1.11

—

VLCD = 0x07

1.07

1.11

1.14

—

VLCD = 0x08

1.10

1.14

1.18

—

VLCD = 0x09

1.13

1.17

1.21

VLCD = 0x0A

1.16

1.21

1.25

—

VLCD = 0x0B

1.20

1.24

1.28

—

VLCD = 0x0C

1.23

1.27

1.32

—

VLCD = 0x0D

1.26

1.31

1.35

—

Double output voltage

VL2

C1 to C5*1 = 0.47 µF

2 × VL1 -

2 × VL1

+ 5%

—

Triple output voltage

VL3

C1 to C5*1 = 0.47 µF

3 × VL1 -

3 × VL1

+ 6%

—

Quadruple output voltage

VL4*5

C1 to C5*1 = 0.47 µF

4 × VL1 -

4 × VL1

+ 6%

—

Reference voltage setup

time*3

tVL1S

—

Figure

2.71

Voltage boost wait time*4

tVLWT

—

500

—

Figure

2.71

Note 1. This is a capacitor that is connected between the voltage pins that are used to drive the LCD.

C1: A capacitor connected between CAPH and CAPL

C2: A capacitor connected between VL1 and GND

C3: A capacitor connected between VL2 and GND

C4: A capacitor connected between VL3 and GND

C5: A capacitor connected between VL4 and GND

C1 = C2 = C3 = C4 = C5 = 0.47 µF ±30%

Note 2. Bit [7] (MDSET[2]) of register VLCD is set to 0 and bits [7:6] (MDSET[1:0]) of register LCDM0 are set to 01 for internal voltage

boosting method (VL1 reference), and bits [4:0] (VLCD4-0) of register VLCD are used for voltage variation setting.

Note 3. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal

voltage boosting method is selected (by setting the MDSET[1:0] bits of the LCDM0 register to 01b and MDSET[2] of the register

VLCD to 0) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1).

Note 4. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).

Note 5. VL4 must be 3.6 V or lower.

2.12.3

Internal Voltage Boosting Method (VL2 Reference)

(1) 1/3 bias method

Table 2.72

Internal voltage boosting method LCD characteristics (3) (1 of 2)

Conditions: VCC = AVCC = VL2 (Max) + 0.1 to 3.6 V, VSS = AVSS = 0 V

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Test conditions

Half output voltage

VL1

C1 to C4*1 = 0.47 µF

1/2 ×

VL2 -

1/2 ×

VL2

1/2 ×

VL2 +

—

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 103 of 125

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