RA4L1 datasheet(97/125 Pages) RENESAS

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Table 2.63

Power-on reset circuit and voltage detection circuit characteristics (1) (2 of 2)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

Voltage detection

circuit (LVD2)*3

When power supply rise

Vdet2_0

3.06

3.19

3.32

Figure 2.69

When power supply fall

3.00

3.13

3.26

When power supply rise

Vdet2_1

2.86

2.98

3.10

When power supply fall

2.80

2.92

3.04

When power supply rise

Vdet2_2

2.66

2.78

2.90

When power supply fall

2.60

2.71

2.82

When power supply rise

Vdet2_3

2.46

2.57

2.68

When power supply fall

2.40

2.50

2.60

When power supply rise

Vdet2_4

2.26

2.36

2.46

Figure 2.69

When power supply fall

2.20

2.30

2.40

When power supply rise

Vdet2_5

2.06

2.15

2.24

When power supply fall

2.00

2.09

2.18

When power supply rise

Vdet2_6

1.86

1.94

2.02

When power supply fall

1.80

1.88

1.96

When power supply rise

Vdet2_7

1.66

1.73

1.80

When power supply fall

1.60

1.67

1.74

Note:

These characteristics apply when noise is not superimposed on the power supply.

Note 1. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL0[1:0] bits.

Note 2. # in the symbol Vdet1_# denotes the value of the LVD1CMPCR.LVD1LVL[3:0] bits.

Note 3. # in the symbol Vdet2_# denotes the value of the LVD2CMPCR.LVD2LVL[2:0] bits.

Table 2.64

Power-on reset circuit and voltage detection circuit characteristics (2) (1 of 2)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

Wait time after power-on

reset cancellation

LVD0: enable

tPOR

—

4.9

—

LVD0: disable

tPOR

—

4.2

—

Wait time after voltage

monitor 0, 1, 2 reset

cancellation

LVD0: enable*1

tLVD0,1,2

—

0.94

—

LVD0: disable*2

tLVD1,2

—

0.25

—

Power-on reset response delay time*3

tdet

—

500

µs

Figure 2.65, Figure 2.66

LVD0 response delay time*3

tdet

—

500

µs

Figure 2.67

LVD1 response delay time*3

tdet

—

600

µs

Figure 2.68

LVD2 response delay time*3

tdet

—

600

µs

Figure 2.69

Minimum VCC down time POR

tVOFF

500

—

µs

Figure 2.65

LVD0

300

—

µs

Figure 2.67

LVD1

300

—

µs

Figure 2.68

LVD2

600

—

µs

Figure 2.69

Power-on reset enable time

tW (POR)

—

Figure 2.66, VCC = below 1.0

LVD1 operation stabilization time (after LVD1 is

enabled)

Td (E-A)

—

350

µs

Figure 2.68

LVD2 operation stabilization time (after LVD2 is

enabled)

Td (E-A)

—

600

µs

Figure 2.69

Hysteresis width (POR)

VPORH

—

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 97 of 125

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