RA4L1 datasheet(36/125 Pages) RENESAS

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Table 2.11

Middle-speed mode current

Parameter

Symbol

Typ

Max

Unit

Test conditions

Normal mode

All peripheral clocks enabled, and cache

disable. While (1) code is executing from flash

ICC*1

4.38

—

ICLK = 8 MHz

PCLKA = 8 MHz

PCLKB = 8 MHz

PCLKC = 8 MHz

PCLKD = 8 MHz

FCLK = 8 MHz

All peripheral clocks disabled, and cache

disable. While (1) code is executing from flash*2

1.79

—

Sleep mode

All peripheral clocks enabled, and cache

disable.

3.40

—

All peripheral clocks disabled, and cache

disable.*2

0.81

—

Increase during BGO operation*3

Note:

Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note:

This does not include the BGO operation.

Note:

The clock source is MOCO.

Note 1. ICC depends on f (ICLK) as follows (reference data).

ICC Typ. = 0.49 × f + 0.48 (normal operation, all peripheral clocks disabled and cache disabled)

Note 2. PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (125 kHz).

Note 3. This is the increase for programming or erasure of the flash memory for data storage during program execution.

Table 2.12

Low-speed mode current

Parameter

Symbol

Typ

Max

Unit

Test conditions

Normal mode

All peripheral clocks enabled, and cache

disable. While (1) code is executing from flash

ICC*1

1.10

—

ICLK = 1 MHz

PCLKA = 1 MHz

PCLKB = 1 MHz

PCLKC = 1 MHz

PCLKD = 1 MHz

FCLK = 1 MHz

All peripheral clocks disabled, and cache

disable. While (1) code is executing from flash*2

0.33

—

Sleep mode

All peripheral clocks enabled, and cache

disable.

0.94

—

All peripheral clocks disabled, and cache

disable.*2

0.22

—

Note:

Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note:

This does not include the BGO operation.

Note:

The clock source is MOSC.

Note 1. ICC depends on f (ICLK) as follows (reference data).

ICC Typ. = 0.33 × f + 0.02 (normal operation, all peripheral clocks disabled and cache disabled)

Note 2. PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (15.625 kHz).

Table 2.13

Subosc-speed mode current

Parameter

Symbol

Typ

Max

Unit

Test conditions

Normal mode

All peripheral clocks enabled, and cache

disable. While (1) code is executing from flash

ICC

—

µA

ICLK = 32.768 kHz

PCLKA = 32.768 kHz

PCLKB = 32.768 kHz

PCLKC = 32.768 kHz

PCLKD = 32.768 kHz

FCLK = 32.768 kHz

All peripheral clocks disabled, and cache

disable. While (1) code is executing from flash*1

8.73

—

Sleep mode

All peripheral clocks enabled, and cache

disable.

—

All peripheral clocks disabled, and cache

disable.*1

4.26

—

Note:

Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note:

This does not include the BGO operation.

Note:

The clock source is LOCO.

Note 1. PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (512 Hz).

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 36 of 125

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