RA4L1 datasheet(43/125 Pages) RENESAS

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Table 2.21

Outline of operation for each unit (2 of 2)

Peripheral

Outline of operation

RTC

RTC is operating with LOCO.

WDT

WDT is operating with PCLKB.

IWDT

IWDT is operating with IWDTCLK.

USBFS

Transfer type is set to bulk transfer. USBFS is operating using Full-speed transfer (12 Mbps).

SCI

SCI is transmitting data in clock synchronous mode.

IrDA

SCI is transmitting data in clock asynchronous mode. IrDA is only clear module stop bit.

IIC

Communication format is set to I2C-bus format. IIC is transmitting data in master mode.

I3C

Communication format is set to I3C SDR format. I3C is transmitting data in master mode (5 MHz).

CANFD

CANFD is transmitting and receiving data in self-test mode 1.

SPI

SPI mode is set to SPI operation (4-wire method). SPI master/slave mode is set to master mode. SPI is transmitting

32-bit width data.

QSPI

QSPI is issuing Fast Read Quad I/O Instruction.

SSIE

Communication mode is set to Master. System word length is set to 32 bits. Data word length is set to 20 bits. SSIE is

transmitting data using I2S format.

UARTA

UARTA is transmitting 8-bit width data.

ACMPLP

ACMPLP is operating.

ADC12

Resolution is set to 12-bit accuracy. Data register is set to A/D-converted value addition mode. ADC12 is converting

the analog input in continuous scan mode.

DAC12

DAC12 is outputting the conversion result while updating the value of data register.

CTSU

CTSU is operating in self-capacitance single scan mode.

SLCDC

SLCDC is operating in A wave, 1/2 bias method, 2-time slice and External resistance division method

ELC

Only clear module stop bit.

RSIP-E04A

RSIP is doing self-test operation.

CRC

CRC is generating CRC code using 32-bit CRC32-C polynomial.

DOC

DOC is operating in data comparison mode.

CAC

Measurement target clocks is set to PCLKB. Measurement reference clocks is set to PCLKB. CAC is measuring the

clock frequency accuracy.

DMAC

Bit length of transfer data is set to 32 bits. Transfer mode is set to block transfer mode. DMAC is transferring data from

SRAM0 to SRAM0.

DTC

Bit length of transfer data is set to 32 bits. Transfer mode is set to block transfer mode. DTC is transferring data from

SRAM0 to SRAM0.

2.3

AC Characteristics

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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