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ADIN1300CCPZ-R7 Folha de dados(PDF) 11 Page - Analog Devices

Nome de Peças ADIN1300CCPZ-R7
Descrição Electrónicos  Robust, Industrial, Low Latency and Low Power 10 Mbps
PDF  79 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

ADIN1300CCPZ-R7 Folha de dados(HTML) 11 Page - Analog Devices

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Data Sheet
ADIN1300
Rev. 0 | Page 11 of 79
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
TXD_1
2
TXD_2
3
TXD_3
4
DVDD_0P9
5
GND
6
CLK25_REF
7
RESET_N
8
XTAL_O
9
XTAL_I/CLK_IN/REF_CLK
10
REXT
23
MDC
24
MDIO
25
VDDIO
26
LINK_ST/PHY_CFG1
27
GP_CLK/RX_ER/MDIX_MODE
28
DVDD_0P9
29
RXD_3/PHYAD_3
30
RXD_2/PHYAD_2
22
INT_N/CRS
21
LED_0/COL/TX_ER/PHY_CFG0
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
ADIN1300
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. THE LFCSP HAS AN EXPOSED PAD THAT MUST BE SOLDERED TO A
METAL PLATE ON THE PCB FOR MECHANICAL REASONS AND TO GND. A 4 × 4 ARRAY
OF THERMAL VIAS BENEATH THE EXPOSED GND PAD IS ALSO REQUIRED.
2. THE LFCSP ALSO HAS TWO KEEPOUT AREAS TO THE TOP AND BOTTOM OF THE
EXPOSED PAD. NO PCB TRACES OR VIAS CAN BE USED IN THESE AREAS.
Figure 10. Pin Configuration
Table 13. Pin Function Descriptions
Pin No.
Mnemonic
Description
Clock Interface
8
XTAL_O
Second Terminal for Crystal Connection. If using a single-ended reference clock on
XTAL_I/CLK_IN/REF_CLK, leave XTAL_O open circuit.
9
XTAL_I/CLK_IN/REF_CLK
Input for Crystal (XTAL_I).
Single-Ended 25 MHz Reference Clock (CLK_IN).
50 MHz RMII Reference Clock Input in RMII Mode (REF_CLK).
Management
Interface
22
INT_N/CRS
Management Interface Interrupt Pin Output (INT_N). Active low output. A low on INT_N
indicates an unmasked management interrupt. This pin requires a 1.5 kΩ pull-up
resistor to VDDIO.
MII Carrier Sense Output (CRS). Indicates the presence of a carrier to MAC.
23
MDC
Management Data Clock Input up to 5.5 MHz.
24
MDIO
Management Data Open-Drain Input/Output Synchronous to the MDC Clock. This pin
requires a 1.5 kΩ pull-up resistor to VDDIO.
Reset
7
RESET_N
Active Low Input. Hold low for >10 μs. This pin requires a1 kΩ pull-up resistor to
AVDD_3P3.
Media Dependent
Interface (MDI)
12
MDI_0_P
Transmit/Receive Differential Pair 0 Supporting 10 Mbps, 100 Mbps, and 1 Gbps.
13
MDI_0_N
Transmit/Receive Differential Pair 0 Supporting 10 Mbps, 100 Mbps, and 1 Gbps.
14
MDI_1_P
Transmit/Receive Differential Pair 1 Supporting 10 Mbps, 100 Mbps, and 1 Gbps.
15
MDI_1_N
Transmit/Receive Differential Pair 1 Supporting 10 Mbps, 100 Mbps, and 1 Gbps.
16
MDI_2_P
Transmit/Receive Differential Pair 2 for 1000BASE-T Mode. Unused in other modes.
17
MDI_2_N
Transmit/Receive Differential Pair 2 for 1000BASE-T Mode. Unused in other modes.



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