ADIN1300CCPZ-R7 datasheet(67/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 67 of 79

LPI Wake Error Count Register

Address: 0xA000, Reset: 0x0000, Name: LPI_WAKE_ERR_CNT

This address corresponds to the EEE wake error counter register specified in Clause 45.2.3.10 of IEEE Standard 802.3, which in the IEEE

standard is at MMD Register Address 3.22.

Table 98. Bit Descriptions for LPI_WAKE_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

LPI_WAKE_ERR_CNT

This bit field counts wake time faults where the PHY fails to complete its normal wake

sequence within the time required. This field self clears upon reading.

0x0

Base 1000 Retrain Enable Register

Address: 0xA001, Reset: 0x0000, Name: B_1000_RTRN_EN

This register allows 1000BASE-T retrain to be enabled. When 1000BASE-T retrain is enabled and the receiver status becomes not okay,

the PHY retrains. During this time, the link remains up but it is not possible to transmit or receive data. When 1000BASE-T retrain is

disabled and the receiver status becomes not okay, the PHY drops the link.

Table 99. Bit Descriptions for B_1000_RTRN_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

B_1000_RTRN_EN

When set, this bit enables 1000BASE-T retrain.

0x0

R/W

Clause 40.4.6.1 of Standard 802.3 requires a PHY that is operating in 1000BASE-T mode to

retrain if it detects that its receiver status is not okay. Such a retrain prevents data from

being transmitted or received for a long period, but does not cause the LINK_STAT_LAT bit

in the direct address map to latch low.

When B_1000_RTRN_EN is clear, 1000BASE-T retrain is disabled. In this case, when the

receiver status becomes not okay, it always results in the link dropping.

1: 1000BASE-T retrain is enabled.

0: 1000BASE-T retrain is disabled.

Base 10e Enable Register

Address: 0xB403, Reset: 0x0001, Name: B_10_E_EN

When set, this register enables 10BASE-Te operation. 10BASE-Te is a variant of 10BASE-T that transmits at a lower voltage level.

Table 100. Bit Descriptions for B_10_E_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

B_10_E_EN

10BASE-Te. When set, this bit enables 10BASE-Te operation, this is the default operation of the

device. 10BASE-Te is a variant of 10BASE-T that transmits at a lower voltage level.

0x1

R/W

10BASE-T Transmit Test Mode Register

Address: 0xB412, Reset: 0x0000, Name: B_10_TX_TST_MODE

This register provides the ability to transmit a 10BASE-T test signal.

Table 101. Bit Descriptions for B_10_TX_TST_MODE

Bits

Bit Name

Description

Reset

Access

[15:3]

RESERVED

Reserved.

0x0

[2:0]

B_10_TX_TST_MODE

The PHY provides the ability to transmit a 10BASE-T test signal consisting of either a

5 MHz or a 10 MHz square wave.

0x0

R/W

111: reserved.

110: reserved.

101: reserved.

100: transmit 5 MHz square wave on Dimension 1.

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