ADIN1300CCPZ-R7 datasheet(49/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 49 of 79

Bits

Bit Name

Description

Reset

Access

MAN_MDIX

When this bit is set and the AUTO_MDI_EN bit is clear, the PHY operates in the MDIX

configuration. In this configuration, no crossover is implemented and the logical pairs of the

PCS correspond to the physical pairs of the AFE. When this bit is clear and the AUTO_MDI_EN

bit is clear, the PHY operates in the MDI configuration and crossovers the pairs. If the

AUTO_MDI_EN bit is set, the MAN_MDIX bit determines the MDI or MDIX preference option.

0x0

R/W

1: operate in MDIX configuration.

0: operate in MDI configuration.

[8:3]

RESERVED

Reserved.

0x0

DIAG_CLK_EN

Enable PHY Diagnostics Clock. This clock is required for certain diagnostic functions within

the PHY, for example, the frame generator/checker.

0x0

R/W

1: enable PHY diagnostics clock.

0: disable PHY diagnostics clock.

[1:0]

RESERVED

Reserved.

0x2

R/W

PHY Control Status 1 Register

Address: 0x0013, Reset: 0x1041, Name: PHY_CTRL_STATUS_1

This register provides access to PHY loopback control bits.

Table 46. Bit Descriptions for PHY_CTRL_STATUS_1

Bits

Bit Name

Description

Reset

Access

[15:13]

RESERVED

Reserved.

0x0

R/W

LB_ALL_DIG_SEL

Setting this bit selects all digital loopback. This loops the data within the PHY at the analog/

digital boundary so that data received on the MAC interface TXD_x pins is looped back to

the RXD_x pins. This requires the IEEE loopback bit (Register 0x0000, Bit 14) to be set.

0x1

R/W

RESERVED

Reserved.

0x0

LB_LD_SEL

Setting this bit selects line driver loopback. If this register bit is set, every time the loopback

bit is set the PHY enters line driver loopback mode. In line driver loopback mode, leave the

MDI pins open to create a large impedance mismatch. The PHY can then operate by

receiving the reflection from its own transmission.

0x0

R/W

LB_REMOTE_EN

Setting this bit enables remote loopback. This requires a link up with a remote PHY and it

loops the data received from the remote PHY back to the remote PHY using all of the

digital and analog circuitry of the PHY.

0x0

R/W

ISOLATE_RX

Setting this bit suppresses data being sent to the MAC during loopback.

0x0

R/W

LB_EXT_EN

Setting this bit enables external cable loopback. This requires an external cable with Pair 0

and Pair 1 and Pair 2 and Pair 3 shorted together to provide an analog loopback at the end

of the cable. All of the digital and analog circuitry of the PHY and the signal processing is

adjusted so that the transmitted signal is not cancelled. The IEEE loopback bit

(Register 0x0000, Bit 14) must not be set.

0x0

R/W

LB_TX_SUP

Setting this bit suppresses the transmit signal at the MDI pins in all digital loopback.

0x1

R/W

[5:1]

RESERVED

Reserved.

0x0

LB_MII_LS_OK

Setting this bit sets the link status signal to okay during MII loopback.

0x1

R/W

Receive Error Count Register

Address: 0x0014, Reset: 0x0000, Name: RX_ERR_CNT

The receive error counter register is used to access the receive error counter associated with the frame checker in the PHY.

Table 47. Bit Descriptions for RX_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

RX_ERR_CNT

This is the receive error counter associated with the frame checker in the PHY. Note that this bit

is self clearing upon reading.

0x0

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